Author: Armin Rigo <ar...@tunes.org>
Branch:
Changeset: r73201:7a2fd8406fbd
Date: 2014-08-30 12:09 +0200
http://bitbucket.org/pypy/pypy/changeset/7a2fd8406fbd/
Log: Add LDREX, STREX, DMB instructions, needed for lock manipulation
diff --git a/rpython/jit/backend/arm/codebuilder.py
b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -318,6 +318,23 @@
| (rd & 0xF) << 12
| imm16 & 0xFFF)
+ def LDREX(self, rt, rn, c=cond.AL):
+ self.write32(c << 28
+ | 0x01900f9f
+ | (rt & 0xF) << 12
+ | (rn & 0xF) << 16)
+
+ def STREX(self, rd, rt, rn, c=cond.AL):
+ """rd must not be the same register as rt or rn"""
+ self.write32(c << 28
+ | 0x01800f90
+ | (rt & 0xF)
+ | (rd & 0xF) << 12
+ | (rn & 0xF) << 16)
+
+ def DMB(self):
+ self.write32(0xf57ff05f)
+
DIV = binary_helper_call('int_div')
MOD = binary_helper_call('int_mod')
UDIV = binary_helper_call('uint_div')
diff --git a/rpython/jit/backend/arm/test/test_instr_codebuilder.py
b/rpython/jit/backend/arm/test/test_instr_codebuilder.py
--- a/rpython/jit/backend/arm/test/test_instr_codebuilder.py
+++ b/rpython/jit/backend/arm/test/test_instr_codebuilder.py
@@ -187,6 +187,18 @@
self.cb.MOVT_ri(r.r3.value, 0xFFFF, conditions.NE)
self.assert_equal("MOVTNE r3, #65535")
+ def test_ldrex(self):
+ self.cb.LDREX(r.r10.value, r.r11.value)
+ self.assert_equal('LDREX r10, [r11]')
+
+ def test_strex(self):
+ self.cb.STREX(r.r9.value, r.r1.value, r.r14.value, conditions.NE)
+ self.assert_equal('STREXNE r9, r1, [r14]')
+
+ def test_dmb(self):
+ self.cb.DMB()
+ self.assert_equal('DMB')
+
def test_size_of_gen_load_int():
for v, n in [(5, 4), (6, 4), (7, 2)]:
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