Author: Alex Gaynor <alex.gay...@gmail.com>
Branch:
Changeset: r73559:b126182576d1
Date: 2014-09-16 11:32 -0700
http://bitbucket.org/pypy/pypy/changeset/b126182576d1/
Log: merged upstream
diff --git a/rpython/jit/backend/arm/callbuilder.py
b/rpython/jit/backend/arm/callbuilder.py
--- a/rpython/jit/backend/arm/callbuilder.py
+++ b/rpython/jit/backend/arm/callbuilder.py
@@ -92,7 +92,8 @@
self.mc.LDR_ri(r.r7.value, r.r5.value)
# change 'rpy_fastgil' to 0 (it should be non-zero right now)
- self.mc.DMB()
+ if self.asm.cpu.cpuinfo.arch_version >= 7:
+ self.mc.DMB()
self.mc.gen_load_int(r.r6.value, fastgil)
self.mc.MOV_ri(r.ip.value, 0)
self.mc.STR_ri(r.ip.value, r.r6.value)
@@ -112,7 +113,8 @@
self.mc.STREX(r.r3.value, r.ip.value, r.r6.value, c=c.EQ)
# try to claim the lock
self.mc.CMP_ri(r.r3.value, 0, cond=c.EQ) # did this succeed?
- self.mc.DMB()
+ if self.asm.cpu.cpuinfo.arch_version >= 7:
+ self.mc.DMB()
# the success of the lock acquisition is defined by
# 'EQ is true', or equivalently by 'r3 == 0'.
#
diff --git a/rpython/jit/backend/arm/codebuilder.py
b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -333,6 +333,8 @@
| (rn & 0xF) << 16)
def DMB(self):
+ # ARMv7 only. I guess ARMv6 CPUs cannot be used in symmetric
+ # multi-processing at all? That would make this instruction unneeded.
# note: 'cond' is only permitted on Thumb here, but don't
# write literally 0xf57ff05f, because it's larger than 31 bits
c = cond.AL
diff --git a/rpython/jit/backend/arm/instructions.py
b/rpython/jit/backend/arm/instructions.py
--- a/rpython/jit/backend/arm/instructions.py
+++ b/rpython/jit/backend/arm/instructions.py
@@ -142,6 +142,7 @@
#'VCVT' : {'opc1':0xB, 'opc2':0xE, 'opc3':0x1, 'base': False},
}
+# ARMv7 only
simd_instructions_3regs = {
'VADD_i64': {'A': 0x8, 'B': 0, 'U': 0},
'VSUB_i64': {'A': 0x8, 'B': 0, 'U': 1},
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