Author: Richard Plangger <r...@pasra.at>
Branch: vecopt2
Changeset: r77123:0a3e47384c29
Date: 2015-04-23 11:13 +0200
http://bitbucket.org/pypy/pypy/changeset/0a3e47384c29/
Log: wrapping all parameters passed to the assembler (from regalloc) in
imm moved try_disable_unroll one layer down to optimize_trace. it is
now easier to access user parameters in optimzie_trace routine
(passing warmstate)
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2419,17 +2419,19 @@
def genop_vec_getarrayitem_raw(self, op, arglocs, resloc):
# considers item scale (raw_load does not)
- base_loc, ofs_loc, size_loc, ofs, sign, integer, aligned = arglocs
+ base_loc, ofs_loc, size_loc, ofs, integer_loc, aligned_loc = arglocs
scale = get_scale(size_loc.value)
src_addr = addr_add(base_loc, ofs_loc, ofs.value, scale)
- self._vec_load(resloc, src_addr, integer, aligned)
+ self._vec_load(resloc, src_addr, integer_loc.value,
+ size_loc.value, aligned_loc.value)
def genop_vec_raw_load(self, op, arglocs, resloc):
- base_loc, ofs_loc, size_loc, ofs, sign, integer, aligned = arglocs
+ base_loc, ofs_loc, size_loc, ofs, integer_loc, aligned_loc = arglocs
src_addr = addr_add(base_loc, ofs_loc, ofs.value, 0)
- self._vec_load(resloc, src_addr, integer, aligned)
+ self._vec_load(resloc, src_addr, integer_loc.value,
+ size_loc.value, aligned_loc.value)
- def _vec_load(self, resloc, src_addr, integer, aligned):
+ def _vec_load(self, resloc, src_addr, integer, itemsize, aligned):
if integer:
if aligned:
raise NotImplementedError
@@ -2437,37 +2439,40 @@
else:
self.mc.MOVDQU(resloc, src_addr)
else:
- if size == 8: # TODO is there a constant for double floating point
size?
- self.mc.MOVSD(resloc, source_addr)
+ if itemsize == 8: # TODO is there a constant for double floating
point size?
+ self.mc.MOVSD(resloc, src_addr)
else:
raise NotImplementedError
def genop_discard_vec_setarrayitem_raw(self, op, arglocs):
# considers item scale (raw_store does not)
- base_loc, ofs_loc, value_loc, size_loc, baseofs, integer, aligned =
arglocs
+ base_loc, ofs_loc, value_loc, size_loc, baseofs, integer_loc,
aligned_loc = arglocs
scale = get_scale(size_loc.value)
dest_loc = addr_add(base_loc, ofs_loc, baseofs.value, scale)
- self._vec_store(dest_loc, value_loc, integer, aligned)
+ self._vec_store(dest_loc, value_loc, integer_loc.value,
+ size_loc.value, aligned_loc.value)
def genop_discard_vec_raw_store(self, op, arglocs):
- base_loc, ofs_loc, value_loc, size_loc, baseofs, integer, aligned =
arglocs
+ base_loc, ofs_loc, value_loc, size_loc, baseofs, integer_loc,
aligned_loc = arglocs
dest_loc = addr_add(base_loc, ofs_loc, baseofs.value, 0)
- self._vec_store(dest_loc, value_loc, integer, aligned)
+ self._vec_store(dest_loc, value_loc, integer_loc.value,
+ size_loc.value, aligned_loc.value)
- def _vec_store(self, dest_loc, value_loc, integer, aligned):
+ def _vec_store(self, dest_loc, value_loc, integer, itemsize, aligned):
if integer:
if aligned:
raise NotImplementedError
else:
self.mc.MOVDQU(dest_loc, value_loc)
else:
- if size == 8: # TODO is there a constant for double floating point
size?
+ if itemsize == 8: # TODO is there a constant for double floating
point size?
self.mc.MOVSD(dest_loc, value_loc)
else:
raise NotImplementedError
def genop_vec_int_add(self, op, arglocs, resloc):
- loc0, loc1, itemsize = arglocs
+ loc0, loc1, itemsize_loc = arglocs
+ itemsize = itemsize_loc.value
if itemsize == 4:
self.mc.PADDD(loc0, loc1)
elif itemsize == 8:
@@ -2475,7 +2480,7 @@
else:
raise NotImplementedError
- def genop_vec_int_signext(self, op):
+ def genop_vec_int_signext(self, op, arglocs, resloc):
pass
# ________________________________________
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -224,7 +224,7 @@
def load_xmm_aligned_16_bytes(self, var, forbidden_vars=[]):
# Load 'var' in a register; but if it is a constant, we can return
# a 16-bytes-aligned ConstFloatLoc.
- if isinstance(var, Const):
+ if isinstance(var, ConstInt):
return self.xrm.convert_to_imm_16bytes_align(var)
else:
return self.xrm.make_sure_var_in_reg(var, forbidden_vars)
@@ -1464,7 +1464,7 @@
descr = op.getdescr()
assert not descr.is_array_of_pointers() and \
not descr.is_array_of_structs()
- itemsize, ofs, sign = unpack_arraydescr(descr)
+ itemsize, ofs, _ = unpack_arraydescr(descr)
integer = not descr.is_array_of_floats()
aligned = False
args = op.getarglist()
@@ -1472,7 +1472,7 @@
ofs_loc = self.rm.make_sure_var_in_reg(op.getarg(1), args)
result_loc = self.force_allocate_reg(op.result)
self.perform(op, [base_loc, ofs_loc, imm(itemsize), imm(ofs),
- sign, integer, aligned], result_loc)
+ imm(integer), imm(aligned)], result_loc)
consider_vec_raw_load = consider_vec_getarrayitem_raw
@@ -1480,7 +1480,7 @@
descr = op.getdescr()
assert not descr.is_array_of_pointers() and \
not descr.is_array_of_structs()
- itemsize, ofs, sign = unpack_arraydescr(descr)
+ itemsize, ofs, _ = unpack_arraydescr(descr)
args = op.getarglist()
base_loc = self.rm.make_sure_var_in_reg(op.getarg(0), args)
value_loc = self.make_sure_var_in_reg(op.getarg(2), args)
@@ -1489,17 +1489,18 @@
integer = not descr.is_array_of_floats()
aligned = False
self.perform_discard(op, [base_loc, ofs_loc, value_loc,
- imm(itemsize), imm(ofs), integer, aligned])
+ imm(itemsize), imm(ofs), imm(integer),
imm(aligned)])
consider_vec_raw_store = consider_vec_setarrayitem_raw
def consider_vec_int_add(self, op):
count = op.getarg(2)
+ assert isinstance(count, ConstInt)
itemsize = 16 // count.value
args = op.getarglist()
loc1 = self.xrm.make_sure_var_in_reg(op.getarg(1), args)
loc0 = self.xrm.force_result_in_reg(op.result, op.getarg(0), args)
- self.perform(op, [loc0, loc1, itemsize], loc0)
+ self.perform(op, [loc0, loc1, imm(itemsize)], loc0)
def consider_vec_int_signext(self, op):
# there is not much we can do in this case. arithmetic is
diff --git a/rpython/jit/metainterp/compile.py
b/rpython/jit/metainterp/compile.py
--- a/rpython/jit/metainterp/compile.py
+++ b/rpython/jit/metainterp/compile.py
@@ -115,13 +115,7 @@
metainterp_sd = metainterp.staticdata
jitdriver_sd = metainterp.jitdriver_sd
history = metainterp.history
-
- enable_opts = jitdriver_sd.warmstate.enable_opts
- if try_disabling_unroll:
- if 'unroll' not in enable_opts:
- return None
- enable_opts = enable_opts.copy()
- del enable_opts['unroll']
+ warmstate = jitdriver_sd.warmstate
jitcell_token = make_jitcell_token(jitdriver_sd)
part = create_empty_loop(metainterp)
@@ -134,7 +128,8 @@
try:
start_state = optimize_trace(metainterp_sd, jitdriver_sd, part,
- enable_opts, export_state=True)
+ warmstate, export_state=True,
+ try_disabling_unroll=try_disabling_unroll)
except InvalidLoop:
return None
target_token = part.operations[0].getdescr()
@@ -161,8 +156,9 @@
jumpargs = part.operations[-1].getarglist()
try:
- optimize_trace(metainterp_sd, jitdriver_sd, part, enable_opts,
- start_state=start_state, export_state=False)
+ optimize_trace(metainterp_sd, jitdriver_sd, part, warmstate,
+ start_state=start_state, export_state=False,
+ try_disabling_unroll=try_disabling_unroll)
except InvalidLoop:
return None
@@ -213,9 +209,9 @@
label = part.operations[0]
orignial_label = label.clone()
assert label.getopnum() == rop.LABEL
+ warmstate = jitdriver_sd.warmstate
try:
- optimize_trace(metainterp_sd, jitdriver_sd, part,
- jitdriver_sd.warmstate.enable_opts,
+ optimize_trace(metainterp_sd, jitdriver_sd, part, warmstate,
start_state=start_state, export_state=False)
except InvalidLoop:
# Fall back on jumping to preamble
@@ -225,8 +221,7 @@
[ResOperation(rop.JUMP, inputargs[:],
None, descr=loop_jitcell_token)]
try:
- optimize_trace(metainterp_sd, jitdriver_sd, part,
- jitdriver_sd.warmstate.enable_opts,
+ optimize_trace(metainterp_sd, jitdriver_sd, part, warmstate,
inline_short_preamble=False,
start_state=start_state,
export_state=False)
except InvalidLoop:
@@ -847,8 +842,7 @@
else:
inline_short_preamble = True
try:
- state = optimize_trace(metainterp_sd, jitdriver_sd, new_trace,
- state.enable_opts,
+ state = optimize_trace(metainterp_sd, jitdriver_sd, new_trace, state,
inline_short_preamble, export_state=True)
except InvalidLoop:
debug_print("compile_new_bridge: got an InvalidLoop")
diff --git a/rpython/jit/metainterp/optimizeopt/__init__.py
b/rpython/jit/metainterp/optimizeopt/__init__.py
--- a/rpython/jit/metainterp/optimizeopt/__init__.py
+++ b/rpython/jit/metainterp/optimizeopt/__init__.py
@@ -48,18 +48,26 @@
return optimizations, unroll
-def optimize_trace(metainterp_sd, jitdriver_sd, loop, enable_opts,
+def optimize_trace(metainterp_sd, jitdriver_sd, loop, warmstate,
inline_short_preamble=True, start_state=None,
- export_state=True):
+ export_state=True, try_disabling_unroll=False):
"""Optimize loop.operations to remove internal overheadish operations.
"""
debug_start("jit-optimize")
+
+ enable_opts = warmstate.enable_opts
+ if try_disabling_unroll:
+ if 'unroll' not in enable_opts:
+ return None
+ enable_opts = enable_opts.copy()
+ del enable_opts['unroll']
+
try:
loop.logops = metainterp_sd.logger_noopt.log_loop(loop.inputargs,
loop.operations)
optimizations, unroll = build_opt_chain(metainterp_sd, enable_opts)
- if jitdriver_sd.vectorize:
+ if warmstate.vectorize and jitdriver_sd.vectorize:
optimize_vector(metainterp_sd, jitdriver_sd, loop,
optimizations)
elif unroll:
diff --git a/rpython/jit/metainterp/pyjitpl.py
b/rpython/jit/metainterp/pyjitpl.py
--- a/rpython/jit/metainterp/pyjitpl.py
+++ b/rpython/jit/metainterp/pyjitpl.py
@@ -2135,7 +2135,7 @@
self.seen_loop_header_for_jdindex = -1
# can only emit early exit if liveness is present
# TODO think of a better way later
- if self.framestack[-1].jitcode.liveness.get(0):
+ if self.framestack[-1].jitcode.liveness.get(0, None):
self.generate_guard(rop.GUARD_EARLY_EXIT)
try:
self.interpret()
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