Author: Richard Plangger <[email protected]>
Branch: vecopt2
Changeset: r77122:e78b0edc35c4
Date: 2015-04-22 16:33 +0200
http://bitbucket.org/pypy/pypy/changeset/e78b0edc35c4/
Log: added vec_int_signext to the backend (is ignored and register is
forced)
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2475,6 +2475,9 @@
else:
raise NotImplementedError
+ def genop_vec_int_signext(self, op):
+ pass
+
# ________________________________________
genop_discard_list = [Assembler386.not_implemented_op_discard] * rop._LAST
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -351,7 +351,7 @@
def loc(self, v):
if v is None: # xxx kludgy
return None
- if v.type == FLOAT:
+ if v.type == FLOAT or v.type == VECTOR:
return self.xrm.loc(v)
return self.rm.loc(v)
@@ -1501,6 +1501,14 @@
loc0 = self.xrm.force_result_in_reg(op.result, op.getarg(0), args)
self.perform(op, [loc0, loc1, itemsize], loc0)
+ def consider_vec_int_signext(self, op):
+ # there is not much we can do in this case. arithmetic is
+ # done on the vector register, if there is a wrap around,
+ # it is lost, because the register does not have enough bits
+ # to save it.
+ argloc = self.loc(op.getarg(0))
+ self.force_allocate_reg(op.result, selected_reg=argloc)
+
def consider_guard_early_exit(self, op):
pass
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