Author: Richard Plangger <r...@pasra.at>
Branch: vecopt
Changeset: r77297:786c0adbf389
Date: 2015-05-12 09:51 +0200
http://bitbucket.org/pypy/pypy/changeset/786c0adbf389/

Log:    vector add now passing for double floating points

diff --git a/rpython/jit/backend/x86/assembler.py 
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2549,13 +2549,24 @@
         exec py.code.Source(_source).compile()
     del genop_vec_float_arith
 
-    def genop_vec_unpack(self, op, arglocs, resloc):
+    def genop_vec_box_unpack(self, op, arglocs, resloc):
         loc0, indexloc, sizeloc = arglocs
         size = sizeloc.value
         if size == 4:
             pass
         elif size == 8:
-            self.mc.CMPPD(
+            if indexloc.value == 0:
+                self.mc.UNPCKLPD(resloc, loc0)
+            else:
+                self.mc.UNPCKHPD(resloc, loc0)
+
+    def genop_vec_expand(self, op, arglocs, resloc):
+        loc0, countloc = arglocs
+        count = countloc.value
+        if count == 1:
+            pass
+        elif count == 2:
+            self.mc.MOVDDUP(resloc, loc0)
 
     def genop_vec_int_signext(self, op, arglocs, resloc):
         pass
diff --git a/rpython/jit/backend/x86/regalloc.py 
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -1568,7 +1568,11 @@
         self.perform(op, [loc0, imm(index.value), imm(itemsize)], result)
 
     def consider_vec_expand(self, op):
-        pass
+        count = op.getarg(1)
+        args = op.getarglist()
+        loc0 = self.make_sure_var_in_reg(op.getarg(0), args)
+        result = self.force_allocate_reg(op.result, args)
+        self.perform(op, [loc0, imm(count.value)], result)
 
     def consider_vec_box(self, op):
         # pseudo instruction, needed to create a new variable
diff --git a/rpython/jit/backend/x86/regloc.py 
b/rpython/jit/backend/x86/regloc.py
--- a/rpython/jit/backend/x86/regloc.py
+++ b/rpython/jit/backend/x86/regloc.py
@@ -673,6 +673,12 @@
     MOVDQ = _binaryop('MOVDQ')
     MOVD32 = _binaryop('MOVD32')
     MOVUPS = _binaryop('MOVUPS')
+    MOVDDUP = _binaryop('MOVDDUP')
+
+    UNPCKHPD = _binaryop('UNPCKHPD')
+    UNPCKLPD = _binaryop('UNPCKLPD')
+    UNPCKHPS = _binaryop('UNPCKHPS')
+    UNPCKLPS = _binaryop('UNPCKLPS')
 
     CALL = _relative_unaryop('CALL')
     JMP = _relative_unaryop('JMP')
diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -732,6 +732,11 @@
     MOVUPS_ax = xmminsn(rex_nw, '\x0F\x11', register(2, 8), 
mem_reg_plus_scaled_reg_plus_const(1))
 
     PSRLDQ_xi = xmminsn('\x66\x0F\x73', orbyte(0xd8), mem_reg_plus_const(1))
+    UNPCKLPD_xx = xmminsn('\x66', rex_nw, '\x0F\x14', register(1, 8), 
register(2, 8), '\xC0')
+    UNPCKHPD_xx = xmminsn('\x66', rex_nw, '\x0F\x15', register(1, 8), 
register(2, 8), '\xC0')
+    UNPCKLPS_xx = xmminsn(        rex_nw, '\x0F\x14', register(1, 8), 
register(2, 8), '\xC0')
+    UNPCKHPS_xx = xmminsn(        rex_nw, '\x0F\x15', register(1, 8), 
register(2, 8), '\xC0')
+    MOVDDUP_xx = xmminsn('\xF2', rex_nw, '\x0F\x12', register(1, 8), 
register(2,8), '\xC0')
     # SSE4.1 PEXTRDD_rxi = xmminsn('\x66', rex_nw, '\x0F\x3A\x14', 
register(1,8), register(2), immediate(3,'b'))
     # ------------------------------------------------------------
 
@@ -920,6 +925,7 @@
 define_modrm_modes('XORPS_x*', [rex_nw, '\x0F\x57', register(1, 8)], 
regtype='XMM')
 define_modrm_modes('ANDPD_x*', ['\x66', rex_nw, '\x0F\x54', register(1, 8)], 
regtype='XMM')
 
+# floating point operations (single & double)
 define_modrm_modes('ADDPD_x*', ['\x66', rex_nw, '\x0F\x58', register(1, 8)], 
regtype='XMM')
 define_modrm_modes('ADDPS_x*', [        rex_nw, '\x0F\x58', register(1, 8)], 
regtype='XMM')
 define_modrm_modes('SUBPD_x*', ['\x66', rex_nw, '\x0F\x5C', register(1, 8)], 
regtype='XMM')
@@ -928,6 +934,8 @@
 define_modrm_modes('MULPS_x*', [        rex_nw, '\x0F\x59', register(1, 8)], 
regtype='XMM')
 define_modrm_modes('DIVPD_x*', ['\x66', rex_nw, '\x0F\x5E', register(1, 8)], 
regtype='XMM')
 define_modrm_modes('DIVPS_x*', [        rex_nw, '\x0F\x5E', register(1, 8)], 
regtype='XMM')
+define_modrm_modes('DIVPD_x*', ['\x66', rex_nw, '\x0F\x5E', register(1, 8)], 
regtype='XMM')
+define_modrm_modes('DIVPS_x*', [        rex_nw, '\x0F\x5E', register(1, 8)], 
regtype='XMM')
 
 def define_pxmm_insn(insnname_template, insn_char):
     def add_insn(char, *post):
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