Author: Richard Plangger <r...@pasra.at>
Branch: vecopt
Changeset: r78300:01fbd63c766c
Date: 2015-06-24 17:35 +0200
http://bitbucket.org/pypy/pypy/changeset/01fbd63c766c/

Log:    docu comment

diff --git a/rpython/doc/jit/vectorization.rst 
b/rpython/doc/jit/vectorization.rst
--- a/rpython/doc/jit/vectorization.rst
+++ b/rpython/doc/jit/vectorization.rst
@@ -47,7 +47,8 @@
 ---------------------------
 
 * The only SIMD instruction architecture currently supported is SSE4.1
-* Packed mul for int8,int64 (see PMUL_)
+* Packed mul for int8,int64 (see PMUL_). It would be possible to use 
PCLMULQDQ. Only supported
+  by some CPUs and must be checked in the cpuid.
 * Loop that convert types from int(8|16|32|64) to int(8|16) are not supported 
in
   the current SSE4.1 assembler implementation.
   The opcode needed spans over multiple instructions. In terms of performance
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