Author: Armin Rigo <ar...@tunes.org>
Branch: optimize-cond-call
Changeset: r79436:995518da4059
Date: 2015-09-04 17:51 +0200
http://bitbucket.org/pypy/pypy/changeset/995518da4059/
Log: Fixing the ARM backend, in-progress
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -12,8 +12,7 @@
from rpython.jit.backend.arm.opassembler import ResOpAssembler
from rpython.jit.backend.arm.regalloc import (Regalloc,
CoreRegisterManager, check_imm_arg, VFPRegisterManager,
- operations as regalloc_operations,
- operations_with_guard as regalloc_operations_with_guard)
+ operations as regalloc_operations)
from rpython.jit.backend.llsupport import jitframe, rewrite
from rpython.jit.backend.llsupport.assembler import DEBUG_COUNTER,
debug_bridge, BaseAssembler
from rpython.jit.backend.llsupport.regalloc import get_scale,
valid_addressing_size
@@ -645,8 +644,10 @@
size_excluding_failure_stuff - loop_head)
def _assemble(self, regalloc, inputargs, operations):
+ self.guard_success_cc = c.cond_none
regalloc.compute_hint_frame_locations(operations)
self._walk_operations(inputargs, operations, regalloc)
+ assert self.guard_success_cc == c.cond_none
frame_depth = regalloc.get_final_frame_depth()
jump_target_descr = regalloc.jump_target_descr
if jump_target_descr is not None:
@@ -927,6 +928,7 @@
def _walk_operations(self, inputargs, operations, regalloc):
fcond = c.AL
self._regalloc = regalloc
+ regalloc.operations = operations
while regalloc.position() < len(operations) - 1:
regalloc.next_instruction()
i = regalloc.position()
@@ -935,18 +937,7 @@
opnum = op.getopnum()
if op.has_no_side_effect() and op.result not in regalloc.longevity:
regalloc.possibly_free_vars_for_op(op)
- elif self._regalloc.can_merge_with_next_guard(op, i, operations):
- guard = operations[i + 1]
- assert guard.is_guard()
- arglocs = regalloc_operations_with_guard[opnum](regalloc, op,
- guard, fcond)
- fcond = asm_operations_with_guard[opnum](self, op,
- guard, arglocs, regalloc, fcond)
- assert fcond is not None
- regalloc.next_instruction()
- regalloc.possibly_free_vars_for_op(guard)
- regalloc.possibly_free_vars(guard.getfailargs())
- elif not we_are_translated() and op.getopnum() == -124:
+ if not we_are_translated() and op.getopnum() == -124:
regalloc.prepare_force_spill(op, fcond)
else:
arglocs = regalloc_operations[opnum](regalloc, op, fcond)
@@ -962,6 +953,7 @@
regalloc.free_temp_vars()
regalloc._check_invariants()
self.mc.mark_op(None) # end of the loop
+ regalloc.operations = None
def regalloc_emit_extra(self, op, arglocs, fcond, regalloc):
# for calls to a function with a specifically-supported OS_xxx
@@ -1516,21 +1508,11 @@
raise NotImplementedError(op)
-def notimplemented_op_with_guard(self, op, guard_op, arglocs, regalloc, fcond):
- print "[ARM/asm] %s with guard %s not implemented" % \
- (op.getopname(), guard_op.getopname())
- raise NotImplementedError(op)
-
asm_operations = [notimplemented_op] * (rop._LAST + 1)
-asm_operations_with_guard = [notimplemented_op_with_guard] * (rop._LAST + 1)
asm_extra_operations = {}
for name, value in ResOpAssembler.__dict__.iteritems():
- if name.startswith('emit_guard_'):
- opname = name[len('emit_guard_'):]
- num = getattr(rop, opname.upper())
- asm_operations_with_guard[num] = value
- elif name.startswith('emit_opx_'):
+ if name.startswith('emit_opx_'):
opname = name[len('emit_opx_'):]
num = getattr(EffectInfo, 'OS_' + opname.upper())
asm_extra_operations[num] = value
diff --git a/rpython/jit/backend/arm/conditions.py
b/rpython/jit/backend/arm/conditions.py
--- a/rpython/jit/backend/arm/conditions.py
+++ b/rpython/jit/backend/arm/conditions.py
@@ -13,6 +13,7 @@
GT = 0xC
LE = 0xD
AL = 0xE
+cond_none = -1
opposites = [NE, EQ, CC, CS, PL, MI, VC, VS, LS, HI, LT, GE, LE, GT, AL]
diff --git a/rpython/jit/backend/arm/helper/assembler.py
b/rpython/jit/backend/arm/helper/assembler.py
--- a/rpython/jit/backend/arm/helper/assembler.py
+++ b/rpython/jit/backend/arm/helper/assembler.py
@@ -6,33 +6,32 @@
from rpython.rlib.rarithmetic import r_uint, r_longlong, intmask
from rpython.jit.metainterp.resoperation import rop
+
+def flush_cc(asm, condition, result_loc):
+ # After emitting an instruction that leaves a boolean result in
+ # a condition code (cc), call this. In the common case, result_loc
+ # will be set to 'fp' by the regalloc, which in this case means
+ # "propagate it between this operation and the next guard by keeping
+ # it in the cc". In the uncommon case, result_loc is another
+ # register, and we emit a load from the cc into this register.
+ assert asm.guard_success_cc == c.cond_none
+ if result_loc is r.fp:
+ asm.guard_success_cc = condition
+ else:
+ asm.mc.MOV_ri(result_loc.value, 1, condition)
+ asm.mc.MOV_ri(result_loc.value, 0, c.get_opposite_of(condition))
+
+
def gen_emit_op_unary_cmp(name, true_cond):
- false_cond = c.get_opposite_of(true_cond)
def f(self, op, arglocs, regalloc, fcond):
assert fcond is not None
reg, res = arglocs
self.mc.CMP_ri(reg.value, 0)
- self.mc.MOV_ri(res.value, 1, true_cond)
- self.mc.MOV_ri(res.value, 0, false_cond)
+ flush_cc(self, true_cond, res)
return fcond
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_guard_unary_cmp(name, true_cond):
- false_cond = c.get_opposite_of(true_cond)
- def f(self, op, guard, arglocs, regalloc, fcond):
- assert fcond is not None
- assert guard is not None
- reg = arglocs[0]
- self.mc.CMP_ri(reg.value, 0)
- cond = true_cond
- guard_opnum = guard.getopnum()
- if guard_opnum == rop.GUARD_FALSE:
- cond = false_cond
- return self._emit_guard(guard, arglocs[1:], cond, save_exc=False)
- f.__name__ = 'emit_guard_%s' % name
- return f
-
def gen_emit_op_ri(name, opname):
ri_op = getattr(InstrBuilder, '%s_ri' % opname)
rr_op = getattr(InstrBuilder, '%s_rr' % opname)
@@ -61,8 +60,7 @@
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_cmp_op(name, condition):
- inv = c.get_opposite_of(condition)
+def gen_emit_cmp_op(name, true_cond):
def f(self, op, arglocs, regalloc, fcond):
l0, l1, res = arglocs
@@ -70,32 +68,11 @@
self.mc.CMP_ri(l0.value, imm=l1.getint(), cond=fcond)
else:
self.mc.CMP_rr(l0.value, l1.value, cond=fcond)
- self.mc.MOV_ri(res.value, 1, cond=condition)
- self.mc.MOV_ri(res.value, 0, cond=inv)
+ flush_cc(self, true_cond, res)
return fcond
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_cmp_op_guard(name, true_cond):
- false_cond = c.get_opposite_of(true_cond)
- def f(self, op, guard, arglocs, regalloc, fcond):
- assert guard is not None
- l0 = arglocs[0]
- l1 = arglocs[1]
- assert l0.is_core_reg()
-
- if l1.is_imm():
- self.mc.CMP_ri(l0.value, imm=l1.getint(), cond=fcond)
- else:
- self.mc.CMP_rr(l0.value, l1.value, cond=fcond)
- guard_opnum = guard.getopnum()
- cond = true_cond
- if guard_opnum == rop.GUARD_FALSE:
- cond = false_cond
- return self._emit_guard(guard, arglocs[2:], cond, save_exc=False)
- f.__name__ = 'emit_guard_%s' % name
- return f
-
def gen_emit_float_op(name, opname):
op_rr = getattr(InstrBuilder, opname)
def f(self, op, arglocs, regalloc, fcond):
@@ -113,34 +90,16 @@
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_float_cmp_op(name, cond):
- inv = c.get_opposite_of(cond)
+def gen_emit_float_cmp_op(name, true_cond):
def f(self, op, arglocs, regalloc, fcond):
arg1, arg2, res = arglocs
self.mc.VCMP(arg1.value, arg2.value)
self.mc.VMRS(cond=fcond)
- self.mc.MOV_ri(res.value, 1, cond=cond)
- self.mc.MOV_ri(res.value, 0, cond=inv)
+ flush_cc(self, true_cond, res)
return fcond
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_float_cmp_op_guard(name, true_cond):
- false_cond = c.get_opposite_of(true_cond)
- def f(self, op, guard, arglocs, regalloc, fcond):
- assert guard is not None
- arg1 = arglocs[0]
- arg2 = arglocs[1]
- self.mc.VCMP(arg1.value, arg2.value)
- self.mc.VMRS(cond=fcond)
- cond = true_cond
- guard_opnum = guard.getopnum()
- if guard_opnum == rop.GUARD_FALSE:
- cond = false_cond
- return self._emit_guard(guard, arglocs[2:], cond, save_exc=False)
- f.__name__ = 'emit_guard_%s' % name
- return f
-
class saved_registers(object):
def __init__(self, cb, regs_to_save, vfp_regs_to_save=None):
diff --git a/rpython/jit/backend/arm/helper/regalloc.py
b/rpython/jit/backend/arm/helper/regalloc.py
--- a/rpython/jit/backend/arm/helper/regalloc.py
+++ b/rpython/jit/backend/arm/helper/regalloc.py
@@ -50,42 +50,28 @@
f.__name__ = name
return f
-def prepare_float_op(name=None, base=True, float_result=True, guard=False):
- if guard:
- def f(self, op, guard_op, fcond):
- locs = []
- loc1 = self.make_sure_var_in_reg(op.getarg(0))
- locs.append(loc1)
- if base:
- loc2 = self.make_sure_var_in_reg(op.getarg(1))
- locs.append(loc2)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- if guard_op is None:
- res = self.force_allocate_reg(op.result)
- assert float_result == (op.result.type == FLOAT)
- locs.append(res)
- return locs
- else:
- args = self._prepare_guard(guard_op, locs)
- return args
- else:
- def f(self, op, fcond):
- locs = []
- loc1 = self.make_sure_var_in_reg(op.getarg(0))
- locs.append(loc1)
- if base:
- loc2 = self.make_sure_var_in_reg(op.getarg(1))
- locs.append(loc2)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
- assert float_result == (op.result.type == FLOAT)
- locs.append(res)
- return locs
- if name:
- f.__name__ = name
- return f
+def prepare_unary_op(self, op, fcond):
+ loc1 = self.make_sure_var_in_reg(op.getarg(0))
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ return [loc1, res]
+
+def prepare_two_regs_op(self, op, fcond):
+ loc1 = self.make_sure_var_in_reg(op.getarg(0))
+ loc2 = self.make_sure_var_in_reg(op.getarg(1))
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ return [loc1, loc2, res]
+
+def prepare_float_cmp(self, op, fcond):
+ loc1 = self.make_sure_var_in_reg(op.getarg(0))
+ loc2 = self.make_sure_var_in_reg(op.getarg(1))
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg_or_cc(op.result)
+ return [loc1, loc2, res]
def prepare_op_by_helper_call(name):
def f(self, op, fcond):
@@ -106,43 +92,28 @@
f.__name__ = name
return f
-def prepare_cmp_op(name=None):
- def f(self, op, guard_op, fcond):
- assert fcond is not None
- boxes = list(op.getarglist())
- arg0, arg1 = boxes
- imm_a1 = check_imm_box(arg1)
+def prepare_int_cmp(self, op, fcond):
+ assert fcond is not None
+ boxes = list(op.getarglist())
+ arg0, arg1 = boxes
+ imm_a1 = check_imm_box(arg1)
- l0 = self.make_sure_var_in_reg(arg0, forbidden_vars=boxes)
- if imm_a1:
- l1 = self.convert_to_imm(arg1)
- else:
- l1 = self.make_sure_var_in_reg(arg1, forbidden_vars=boxes)
+ l0 = self.make_sure_var_in_reg(arg0, forbidden_vars=boxes)
+ if imm_a1:
+ l1 = self.convert_to_imm(arg1)
+ else:
+ l1 = self.make_sure_var_in_reg(arg1, forbidden_vars=boxes)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- if guard_op is None:
- res = self.force_allocate_reg(op.result)
- return [l0, l1, res]
- else:
- args = self._prepare_guard(guard_op, [l0, l1])
- return args
- if name:
- f.__name__ = name
- return f
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg_or_cc(op.result)
+ return [l0, l1, res]
-def prepare_op_unary_cmp(name=None):
- def f(self, op, guard_op, fcond):
- assert fcond is not None
- a0 = op.getarg(0)
- assert isinstance(a0, Box)
- reg = self.make_sure_var_in_reg(a0)
- self.possibly_free_vars_for_op(op)
- if guard_op is None:
- res = self.force_allocate_reg(op.result, [a0])
- return [reg, res]
- else:
- return self._prepare_guard(guard_op, [reg])
- if name:
- f.__name__ = name
- return f
+def prepare_unary_cmp(self, op, fcond):
+ assert fcond is not None
+ a0 = op.getarg(0)
+ assert isinstance(a0, Box)
+ reg = self.make_sure_var_in_reg(a0)
+ self.possibly_free_vars_for_op(op)
+ res = self.force_allocate_reg_or_cc(op.result)
+ return [reg, res]
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -5,13 +5,10 @@
from rpython.jit.backend.arm.arch import WORD, DOUBLE_WORD, JITFRAME_FIXED_SIZE
from rpython.jit.backend.arm.helper.assembler import
(gen_emit_op_by_helper_call,
gen_emit_op_unary_cmp,
- gen_emit_guard_unary_cmp,
gen_emit_op_ri,
gen_emit_cmp_op,
- gen_emit_cmp_op_guard,
gen_emit_float_op,
gen_emit_float_cmp_op,
- gen_emit_float_cmp_op_guard,
gen_emit_unary_float_op,
saved_registers)
from rpython.jit.backend.arm.helper.regalloc import check_imm_arg
@@ -160,27 +157,13 @@
emit_op_int_gt = gen_emit_cmp_op('int_gt', c.GT)
emit_op_int_ge = gen_emit_cmp_op('int_ge', c.GE)
- emit_guard_int_lt = gen_emit_cmp_op_guard('int_lt', c.LT)
- emit_guard_int_le = gen_emit_cmp_op_guard('int_le', c.LE)
- emit_guard_int_eq = gen_emit_cmp_op_guard('int_eq', c.EQ)
- emit_guard_int_ne = gen_emit_cmp_op_guard('int_ne', c.NE)
- emit_guard_int_gt = gen_emit_cmp_op_guard('int_gt', c.GT)
- emit_guard_int_ge = gen_emit_cmp_op_guard('int_ge', c.GE)
-
emit_op_uint_le = gen_emit_cmp_op('uint_le', c.LS)
emit_op_uint_gt = gen_emit_cmp_op('uint_gt', c.HI)
emit_op_uint_lt = gen_emit_cmp_op('uint_lt', c.LO)
emit_op_uint_ge = gen_emit_cmp_op('uint_ge', c.HS)
- emit_guard_uint_le = gen_emit_cmp_op_guard('uint_le', c.LS)
- emit_guard_uint_gt = gen_emit_cmp_op_guard('uint_gt', c.HI)
- emit_guard_uint_lt = gen_emit_cmp_op_guard('uint_lt', c.LO)
- emit_guard_uint_ge = gen_emit_cmp_op_guard('uint_ge', c.HS)
-
emit_op_ptr_eq = emit_op_instance_ptr_eq = emit_op_int_eq
emit_op_ptr_ne = emit_op_instance_ptr_ne = emit_op_int_ne
- emit_guard_ptr_eq = emit_guard_instance_ptr_eq = emit_guard_int_eq
- emit_guard_ptr_ne = emit_guard_instance_ptr_ne = emit_guard_int_ne
emit_op_int_add_ovf = emit_op_int_add
emit_op_int_sub_ovf = emit_op_int_sub
@@ -188,9 +171,6 @@
emit_op_int_is_true = gen_emit_op_unary_cmp('int_is_true', c.NE)
emit_op_int_is_zero = gen_emit_op_unary_cmp('int_is_zero', c.EQ)
- emit_guard_int_is_true = gen_emit_guard_unary_cmp('int_is_true', c.NE)
- emit_guard_int_is_zero = gen_emit_guard_unary_cmp('int_is_zero', c.EQ)
-
def emit_op_int_invert(self, op, arglocs, regalloc, fcond):
reg, res = arglocs
@@ -1125,13 +1105,6 @@
emit_op_float_gt = gen_emit_float_cmp_op('float_gt', c.GT)
emit_op_float_ge = gen_emit_float_cmp_op('float_ge', c.GE)
- emit_guard_float_lt = gen_emit_float_cmp_op_guard('float_lt', c.VFP_LT)
- emit_guard_float_le = gen_emit_float_cmp_op_guard('float_le', c.VFP_LE)
- emit_guard_float_eq = gen_emit_float_cmp_op_guard('float_eq', c.EQ)
- emit_guard_float_ne = gen_emit_float_cmp_op_guard('float_ne', c.NE)
- emit_guard_float_gt = gen_emit_float_cmp_op_guard('float_gt', c.GT)
- emit_guard_float_ge = gen_emit_float_cmp_op_guard('float_ge', c.GE)
-
def emit_op_cast_float_to_int(self, op, arglocs, regalloc, fcond):
arg, res = arglocs
assert arg.is_vfp_reg()
diff --git a/rpython/jit/backend/arm/regalloc.py
b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -8,10 +8,12 @@
from rpython.jit.backend.arm import locations
from rpython.jit.backend.arm.locations import imm, get_fp_offset
from rpython.jit.backend.arm.helper.regalloc import (prepare_op_by_helper_call,
- prepare_op_unary_cmp,
+ prepare_unary_cmp,
prepare_op_ri,
- prepare_cmp_op,
- prepare_float_op,
+ prepare_int_cmp,
+ prepare_unary_op,
+ prepare_two_regs_op,
+ prepare_float_cmp,
check_imm_arg,
check_imm_box,
VMEM_imm_size,
@@ -146,6 +148,7 @@
box_types = None # or a list of acceptable types
no_lower_byte_regs = all_regs
save_around_call_regs = r.caller_resp
+ frame_reg = r.fp
def __init__(self, longevity, frame_manager=None, assembler=None):
RegisterManager.__init__(self, longevity, frame_manager, assembler)
@@ -235,6 +238,18 @@
return self.rm.force_allocate_reg(var, forbidden_vars,
selected_reg, need_lower_byte)
+ def force_allocate_reg_or_cc(self, var, forbidden_vars=[]):
+ assert var.type == INT
+ if self.next_op_can_accept_cc(self.operations, self.rm.position):
+ # hack: return the 'fp' location to mean "lives in CC". This
+ # fp will not actually be used, and the location will be freed
+ # after the next op as usual.
+ self.rm.force_allocate_frame_reg(var)
+ return r.fp
+ else:
+ # else, return a regular register (not fp).
+ return self.rm.force_allocate_reg(var)
+
def try_allocate_reg(self, v, selected_reg=None, need_lower_byte=False):
if v.type == FLOAT:
return self.vfprm.try_allocate_reg(v, selected_reg,
@@ -500,55 +515,30 @@
prepare_op_uint_rshift = prepare_op_ri('uint_rshift', imm_size=0x1F,
allow_zero=False, commutative=False)
- prepare_op_int_lt = prepare_cmp_op('int_lt')
- prepare_op_int_le = prepare_cmp_op('int_le')
- prepare_op_int_eq = prepare_cmp_op('int_eq')
- prepare_op_int_ne = prepare_cmp_op('int_ne')
- prepare_op_int_gt = prepare_cmp_op('int_gt')
- prepare_op_int_ge = prepare_cmp_op('int_ge')
+ prepare_op_int_lt = prepare_int_cmp
+ prepare_op_int_le = prepare_int_cmp
+ prepare_op_int_eq = prepare_int_cmp
+ prepare_op_int_ne = prepare_int_cmp
+ prepare_op_int_gt = prepare_int_cmp
+ prepare_op_int_ge = prepare_int_cmp
- prepare_op_uint_le = prepare_cmp_op('uint_le')
- prepare_op_uint_gt = prepare_cmp_op('uint_gt')
+ prepare_op_uint_le = prepare_int_cmp
+ prepare_op_uint_gt = prepare_int_cmp
- prepare_op_uint_lt = prepare_cmp_op('uint_lt')
- prepare_op_uint_ge = prepare_cmp_op('uint_ge')
+ prepare_op_uint_lt = prepare_int_cmp
+ prepare_op_uint_ge = prepare_int_cmp
prepare_op_ptr_eq = prepare_op_instance_ptr_eq = prepare_op_int_eq
prepare_op_ptr_ne = prepare_op_instance_ptr_ne = prepare_op_int_ne
- prepare_guard_int_lt = prepare_cmp_op('guard_int_lt')
- prepare_guard_int_le = prepare_cmp_op('guard_int_le')
- prepare_guard_int_eq = prepare_cmp_op('guard_int_eq')
- prepare_guard_int_ne = prepare_cmp_op('guard_int_ne')
- prepare_guard_int_gt = prepare_cmp_op('guard_int_gt')
- prepare_guard_int_ge = prepare_cmp_op('guard_int_ge')
-
- prepare_guard_uint_le = prepare_cmp_op('guard_uint_le')
- prepare_guard_uint_gt = prepare_cmp_op('guard_uint_gt')
-
- prepare_guard_uint_lt = prepare_cmp_op('guard_uint_lt')
- prepare_guard_uint_ge = prepare_cmp_op('guard_uint_ge')
-
- prepare_guard_ptr_eq = prepare_guard_instance_ptr_eq = prepare_guard_int_eq
- prepare_guard_ptr_ne = prepare_guard_instance_ptr_ne = prepare_guard_int_ne
-
prepare_op_int_add_ovf = prepare_op_int_add
prepare_op_int_sub_ovf = prepare_op_int_sub
- prepare_op_int_is_true = prepare_op_unary_cmp('int_is_true')
- prepare_op_int_is_zero = prepare_op_unary_cmp('int_is_zero')
+ prepare_op_int_is_true = prepare_unary_cmp
+ prepare_op_int_is_zero = prepare_unary_cmp
- prepare_guard_int_is_true = prepare_op_unary_cmp('int_is_true')
- prepare_guard_int_is_zero = prepare_op_unary_cmp('int_is_zero')
-
- def prepare_op_int_neg(self, op, fcond):
- l0 = self.make_sure_var_in_reg(op.getarg(0))
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- resloc = self.force_allocate_reg(op.result)
- return [l0, resloc]
-
- prepare_op_int_invert = prepare_op_int_neg
+ prepare_op_int_neg = prepare_unary_op
+ prepare_op_int_invert = prepare_unary_op
def prepare_op_call(self, op, fcond):
effectinfo = op.getdescr().get_extra_info()
@@ -1271,39 +1261,18 @@
arglocs.append(t)
return arglocs
- prepare_op_float_add = prepare_float_op(name='prepare_op_float_add')
- prepare_op_float_sub = prepare_float_op(name='prepare_op_float_sub')
- prepare_op_float_mul = prepare_float_op(name='prepare_op_float_mul')
- prepare_op_float_truediv =
prepare_float_op(name='prepare_op_float_truediv')
- prepare_op_float_lt = prepare_float_op(float_result=False,
- name='prepare_op_float_lt')
- prepare_op_float_le = prepare_float_op(float_result=False,
- name='prepare_op_float_le')
- prepare_op_float_eq = prepare_float_op(float_result=False,
- name='prepare_op_float_eq')
- prepare_op_float_ne = prepare_float_op(float_result=False,
- name='prepare_op_float_ne')
- prepare_op_float_gt = prepare_float_op(float_result=False,
- name='prepare_op_float_gt')
- prepare_op_float_ge = prepare_float_op(float_result=False,
- name='prepare_op_float_ge')
- prepare_op_float_neg = prepare_float_op(base=False,
- name='prepare_op_float_neg')
- prepare_op_float_abs = prepare_float_op(base=False,
- name='prepare_op_float_abs')
-
- prepare_guard_float_lt = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_lt')
- prepare_guard_float_le = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_le')
- prepare_guard_float_eq = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_eq')
- prepare_guard_float_ne = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_ne')
- prepare_guard_float_gt = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_gt')
- prepare_guard_float_ge = prepare_float_op(guard=True,
- float_result=False, name='prepare_guard_float_ge')
+ prepare_op_float_add = prepare_two_regs_op
+ prepare_op_float_sub = prepare_two_regs_op
+ prepare_op_float_mul = prepare_two_regs_op
+ prepare_op_float_truediv = prepare_two_regs_op
+ prepare_op_float_lt = prepare_float_cmp
+ prepare_op_float_le = prepare_float_cmp
+ prepare_op_float_eq = prepare_float_cmp
+ prepare_op_float_ne = prepare_float_cmp
+ prepare_op_float_gt = prepare_float_cmp
+ prepare_op_float_ge = prepare_float_cmp
+ prepare_op_float_neg = prepare_unary_op
+ prepare_op_float_abs = prepare_unary_op
def _prepare_op_math_sqrt(self, op, fcond):
loc = self.make_sure_var_in_reg(op.getarg(1))
@@ -1327,10 +1296,8 @@
self.force_spill_var(op.getarg(0))
return []
- prepare_op_convert_float_bytes_to_longlong = prepare_float_op(base=False,
-
name='prepare_op_convert_float_bytes_to_longlong')
- prepare_op_convert_longlong_bytes_to_float = prepare_float_op(base=False,
-
name='prepare_op_convert_longlong_bytes_to_float')
+ prepare_op_convert_float_bytes_to_longlong = prepare_unary_op
+ prepare_op_convert_longlong_bytes_to_float = prepare_unary_op
#def prepare_op_read_timestamp(self, op, fcond):
# loc = self.get_scratch_reg(INT)
@@ -1348,22 +1315,12 @@
return [loc1, res]
-def add_none_argument(fn):
- return lambda self, op, fcond: fn(self, op, None, fcond)
-
-
def notimplemented(self, op, fcond):
print "[ARM/regalloc] %s not implemented" % op.getopname()
raise NotImplementedError(op)
-def notimplemented_with_guard(self, op, guard_op, fcond):
- print "[ARM/regalloc] %s with guard %s not implemented" % \
- (op.getopname(), guard_op.getopname())
- raise NotImplementedError(op)
-
operations = [notimplemented] * (rop._LAST + 1)
-operations_with_guard = [notimplemented_with_guard] * (rop._LAST + 1)
for key, value in rop.__dict__.items():
@@ -1374,13 +1331,3 @@
if hasattr(Regalloc, methname):
func = getattr(Regalloc, methname).im_func
operations[value] = func
-
-for key, value in rop.__dict__.items():
- key = key.lower()
- if key.startswith('_'):
- continue
- methname = 'prepare_guard_%s' % key
- if hasattr(Regalloc, methname):
- func = getattr(Regalloc, methname).im_func
- operations_with_guard[value] = func
- operations[value] = add_none_argument(func)
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