Author: Richard Plangger <planri...@gmail.com> Branch: vecopt-merge Changeset: r79817:84a252c28c3b Date: 2015-09-25 09:23 +0200 http://bitbucket.org/pypy/pypy/changeset/84a252c28c3b/
Log: wunderbar! x86 assembler works for all the test_x86vector tests diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py --- a/rpython/jit/backend/x86/assembler.py +++ b/rpython/jit/backend/x86/assembler.py @@ -556,6 +556,7 @@ self.current_clt.allgcrefs, self.current_clt.frame_info) self._check_frame_depth(self.mc, regalloc.get_gcmap()) + bridgestartpos = self.mc.get_relative_pos() self._accum_update_at_exit(arglocs, inputargs, faildescr, regalloc) frame_depth_no_fixed_size = self._assemble(regalloc, inputargs, operations) codeendpos = self.mc.get_relative_pos() @@ -583,7 +584,8 @@ name = "Bridge # %s" % (descr_number,) self.cpu.profile_agent.native_code_written(name, rawstart, fullsize) - return AsmInfo(ops_offset, startpos + rawstart, codeendpos - startpos, rawstart) + print "bridge pos", hex(startpos+rawstart), hex(rawstart+bridgestartpos), startpos + return AsmInfo(ops_offset, startpos + rawstart, codeendpos - startpos, rawstart+bridgestartpos) def stitch_bridge(self, faildescr, target): """ Stitching means that one can enter a bridge with a complete different register @@ -607,6 +609,7 @@ # if accumulation is saved at the guard, we need to update it here! guard_locs = self.rebuild_faillocs_from_descr(faildescr, version.inputargs) bridge_locs = self.rebuild_faillocs_from_descr(bridge_faildescr, version.inputargs) + #import pdb; pdb.set_trace() guard_accum_info = faildescr.rd_accum_list # O(n^2), but usually you only have at most 1 fail argument while guard_accum_info: @@ -636,6 +639,7 @@ rawstart = self.materialize_loop(looptoken) # update the jump to the real trace self._patch_jump_for_descr(rawstart + offset, asminfo.rawstart) + print faildescr, "=>", hex(asminfo.rawstart) # update the guard to jump right to this custom piece of assembler self.patch_jump_for_descr(faildescr, rawstart) diff --git a/rpython/jit/metainterp/compile.py b/rpython/jit/metainterp/compile.py --- a/rpython/jit/metainterp/compile.py +++ b/rpython/jit/metainterp/compile.py @@ -701,7 +701,8 @@ self.rd_pendingfields = other.rd_pendingfields self.rd_virtuals = other.rd_virtuals self.rd_numb = other.rd_numb - self.rd_accum_list = other.rd_accum_list + if other.rd_accum_list: + self.rd_accum_list = other.rd_accum_list.clone() # we don't copy status ST_BUSY_FLAG = 0x01 # if set, busy tracing from the guard diff --git a/rpython/jit/metainterp/resume.py b/rpython/jit/metainterp/resume.py --- a/rpython/jit/metainterp/resume.py +++ b/rpython/jit/metainterp/resume.py @@ -66,6 +66,13 @@ def next(self): return self.prev + def clone(self): + prev = None + if self.prev: + prev = self.prev.clone() + return AccumInfo(prev, self.scalar_position, self.accum_operation, + self.scalar_box, None) + def __repr__(self): return 'AccumInfo(%s,%s,%s,%s,%s)' % (self.prev is None, self.accum_operation, _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit