Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r80536:78a1e03178a0
Date: 2015-11-04 13:43 +0100
http://bitbucket.org/pypy/pypy/changeset/78a1e03178a0/
Log: ironed out issues that took the wrong register. excluding the
scratch register from managed ones and correctly setting the
registers on the cpu now gives the desired result. added int_sub
diff --git a/rpython/jit/backend/zarch/assembler.py
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -102,12 +102,11 @@
# this function is called (see generate_quick_failure()).
ofs = self.cpu.get_ofs_of_frame_field('jf_descr')
ofs2 = self.cpu.get_ofs_of_frame_field('jf_gcmap')
- mc.STG(r.r2, l.addr(ofs, r.SPP))
- mc.STG(r.r3, l.addr(ofs2, r.SPP))
-
self._push_core_regs_to_jitframe(mc)
if withfloats:
self._push_fp_regs_to_jitframe(mc)
+ mc.STG(r.r2, l.addr(ofs, r.SPP))
+ mc.STG(r.r3, l.addr(ofs2, r.SPP))
if exc:
pass # TODO
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -14,6 +14,7 @@
'AGFR': ('rre', ['\xB9','\x18']),
'A': ('rx', ['\x5A']),
'SR': ('rr', ['\x1B']),
+ 'SG': ('rxy', ['\xE3','\x09']),
'SGR': ('rre', ['\xB9','\x09']),
'AY': ('rxy', ['\xE3','\x5A']),
diff --git a/rpython/jit/backend/zarch/opassembler.py
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -16,6 +16,13 @@
else:
self.mc.AGR(l0, l1)
+ def emit_int_sub(self, op, arglocs, regalloc):
+ l0, l1 = arglocs
+ if l1.is_in_pool():
+ self.mc.SG(l0, l1)
+ else:
+ self.mc.SGR(l0, l1)
+
emit_int_le = gen_emit_cmp_op(c.LE)
emit_int_lt = gen_emit_cmp_op(c.LT)
emit_int_gt = gen_emit_cmp_op(c.GT)
diff --git a/rpython/jit/backend/zarch/regalloc.py
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -121,10 +121,8 @@
def ensure_reg(self, box):
if isinstance(box, Const):
- xxx
- loc = self.get_scratch_reg()
- immvalue = self.convert_to_int(box)
- self.assembler.mc.load_imm(loc, immvalue)
+ offset = self.assembler.pool.get_descr_offset(box)
+ return l.pool(offset)
else:
assert box in self.temp_boxes
loc = self.make_sure_var_in_reg(box,
diff --git a/rpython/jit/backend/zarch/registers.py
b/rpython/jit/backend/zarch/registers.py
--- a/rpython/jit/backend/zarch/registers.py
+++ b/rpython/jit/backend/zarch/registers.py
@@ -7,14 +7,15 @@
[r0,r1,r2,r3,r4,r5,r6,r7,r8,
r9,r10,r11,r12,r13,r14,r15] = registers
-MANAGED_REGS = [r0,r2,r3,r4,r5,r6,r7,r8,r9,r10]
+MANAGED_REGS = [r0,r1,r4,r5,r6,r7,r8,r9,r10]
VOLATILES = [r6,r7,r8,r9,r10]
SP = r15
BSP = r12
RETURN = r14
POOL = r13
SPP = r11
-SCRATCH = r1
+SCRATCH = r3
+SCRATCH2 = r2
[f0,f1,f2,f3,f4,f5,f6,f7,f8,
f9,f10,f11,f12,f13,f14,f15] = fpregisters
@@ -26,7 +27,7 @@
# number of registers that need to be saved into the jitframe when
# failing a guard, for example.
ALL_REG_INDEXES = {}
-for _r in MANAGED_REGS:
+for _r in registers:
ALL_REG_INDEXES[_r] = len(ALL_REG_INDEXES)
for _r in MANAGED_FP_REGS:
ALL_REG_INDEXES[_r] = len(ALL_REG_INDEXES) + 1
diff --git a/rpython/jit/backend/zarch/runner.py
b/rpython/jit/backend/zarch/runner.py
--- a/rpython/jit/backend/zarch/runner.py
+++ b/rpython/jit/backend/zarch/runner.py
@@ -23,7 +23,7 @@
frame_reg = r.SP
all_reg_indexes = [-1] * 32
- for _i, _r in enumerate(r.MANAGED_REGS):
+ for _i, _r in enumerate(r.registers):
all_reg_indexes[_r.value] = _i
gen_regs = r.MANAGED_REGS
float_regs = r.MANAGED_FP_REGS
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