Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r81737:d411a9856766
Date: 2016-01-13 10:23 +0100
http://bitbucket.org/pypy/pypy/changeset/d411a9856766/
Log: added to more tests & bug fix: do not use SRLG (logical right shift)
or any other shift with parameters R_1 and R_3 that designate the
same register
diff --git a/rpython/jit/backend/zarch/helper/assembler.py
b/rpython/jit/backend/zarch/helper/assembler.py
--- a/rpython/jit/backend/zarch/helper/assembler.py
+++ b/rpython/jit/backend/zarch/helper/assembler.py
@@ -27,8 +27,10 @@
def gen_emit_shift(func):
def f(self, op, arglocs, regalloc):
- l0, l1 = arglocs
- getattr(self.mc, func)(l0, l0, l1)
+ lr, l0, l1 = arglocs
+ assert lr is not l0
+ getattr(self.mc, func)(lr, l0, l1)
+ f.name = 'emit_shift_' + func
return f
def gen_emit_rr_or_rpool(rr_func, rp_func):
diff --git a/rpython/jit/backend/zarch/helper/regalloc.py
b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -115,9 +115,9 @@
tmp = self.rm.ensure_reg(a1, force_in_reg=True)
l1 = addr(0, tmp)
l0 = self.ensure_reg(a0, force_in_reg=True)
- self.force_result_in_reg(op, a0)
+ lr = self.force_allocate_reg(op)
self.free_op_vars()
- return [l0, l1]
+ return [lr, l0, l1]
def generate_cmp_op(signed=True):
def prepare_cmp_op(self, op):
diff --git a/rpython/jit/backend/zarch/test/test_assembler.py
b/rpython/jit/backend/zarch/test/test_assembler.py
--- a/rpython/jit/backend/zarch/test/test_assembler.py
+++ b/rpython/jit/backend/zarch/test/test_assembler.py
@@ -177,6 +177,16 @@
self.a.jmpto(r.r14)
assert run_asm(self.a) == -1
+ def test_uint_rshift(self):
+ self.a.mc.XGR(r.r4, r.r4)
+ self.a.mc.LGFI(r.r5, loc.imm(63))
+ self.a.mc.NGR(r.r4, r.r5)
+ self.a.mc.LGFI(r.r3, loc.imm(18))
+ self.a.mc.LGFI(r.r2, loc.imm(0xffffffff))
+ self.a.mc.SRLG(r.r2, r.r3, loc.addr(18))
+ self.a.jmpto(r.r14)
+ assert run_asm(self.a) == 0
+
def test_xor(self):
self.a.mc.XGR(r.r2, r.r2)
self.a.jmpto(r.r14)
diff --git a/rpython/jit/backend/zarch/test/test_int.py
b/rpython/jit/backend/zarch/test/test_int.py
--- a/rpython/jit/backend/zarch/test/test_int.py
+++ b/rpython/jit/backend/zarch/test/test_int.py
@@ -16,6 +16,25 @@
cpu = CPU_S390_64(rtyper=None, stats=FakeStats())
cpu.setup_once()
+ def test_uint_rshift(self):
+ code = """
+ [i1]
+ i11 = int_and(i1, 63)
+ i10 = uint_rshift(18, i11)
+ i1402 = int_is_true(i10)
+ guard_false(i1402, descr=faildescr) [] # must NEVER exit with i1 == 0
+ finish(i1402, descr=finishdescr)
+ """
+ finishdescr = BasicFinalDescr(1)
+ faildescr = BasicFailDescr(2)
+ loop = parse(code, namespace={'faildescr': faildescr,
+ 'finishdescr': finishdescr})
+ looptoken = JitCellToken()
+ self.cpu.compile_loop(loop.inputargs, loop.operations, looptoken)
+ deadframe = self.cpu.execute_token(looptoken, 19)
+ fail = self.cpu.get_latest_descr(deadframe)
+ assert fail == finishdescr # ensures that guard is not taken!
+
def test_double_evenodd_pair(self):
code = """
[i0]
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