Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r82059:822ac80ddd23
Date: 2016-02-03 17:43 +0100
http://bitbucket.org/pypy/pypy/changeset/822ac80ddd23/
Log: critical bugfix in gc writebarrier fastpath, simplifications and a
test
diff --git a/rpython/jit/backend/zarch/assembler.py
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -205,7 +205,7 @@
saved_regs = None
saved_fp_regs = None
else:
- # push all volatile registers, push RCS1, and sometimes push RCS2
+ # push all volatile registers, sometimes push RCS2
if withcards:
saved_regs = r.VOLATILES + [RCS2]
else:
@@ -223,8 +223,9 @@
# since the call to write barrier can't collect
# (and this is assumed a bit left and right here, like lack
# of _reload_frame_if_necessary)
- # This trashes r0 and r2, which is fine in this case
+ # This trashes r0 and r1, which is fine in this case
assert argument_loc is not r.r0
+ assert argument_loc is not r.r1
self._store_and_reset_exception(mc, RCS2, RCS3)
if withcards:
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -100,6 +100,7 @@
# OR operations
'OGR': ('rre', ['\xB9','\x81']),
+ 'OGRK': ('rrf_a', ['\xB9','\xE6']),
'OG': ('rxy', ['\xE3','\x81']),
# or one byte and store it back at the op2 position
'OI': ('si', ['\x96']),
diff --git a/rpython/jit/backend/zarch/opassembler.py
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -535,8 +535,7 @@
# So here, we can simply write again a beq, which will be
# taken if GCFLAG_CARDS_SET is still not set.
jns_location = mc.get_relative_pos()
- mc.trap()
- mc.write('\x00'*4)
+ mc.reserve_cond_jump()
#
# patch the 'NE' above
currpos = mc.currpos()
@@ -560,25 +559,23 @@
# compute in SCRATCH the index of the bit inside the byte:
# (index >> card_page_shift) & 7
- # not supported on the development s390x :(, extension is not
installed
- # 0x80 sets zero flag. will store 0 into all selected bits
- # mc.RISBGN(r.SCRATCH, loc_index, l.imm(3), l.imm(0x80 | 63),
l.imm(61))
- mc.SRAG(r.SCRATCH, loc_index, l.addr(n))
- mc.NILL(r.SCRATCH, l.imm(0x7))
+ # 0x80 sets zero flag. will store 0 into all not selected bits
+ mc.RISBGN(r.SCRATCH, loc_index, l.imm(61), l.imm(0x80 | 63),
l.imm(64-n))
# invert the bits of tmp_loc
- mc.XIHF(tmp_loc, l.imm(0xffffFFFF))
- mc.XILF(tmp_loc, l.imm(0xffffFFFF))
+ mc.LCGR(tmp_loc, tmp_loc)
+ #mc.XIHF(tmp_loc, l.imm(0xffffFFFF))
+ #mc.XILF(tmp_loc, l.imm(0xffffFFFF))
- # set SCRATCH to 1 << r2
+ # set SCRATCH to 1 << r1
mc.LGHI(r.SCRATCH2, l.imm(1))
- mc.SLAG(r.SCRATCH2, r.SCRATCH2, l.addr(0,r.SCRATCH))
+ mc.SLAG(r.SCRATCH, r.SCRATCH2, l.addr(0,r.SCRATCH))
# set this bit inside the byte of interest
addr = l.addr(0, loc_base, tmp_loc)
mc.LLGC(r.SCRATCH, addr)
- mc.OGR(r.SCRATCH, r.SCRATCH2)
- mc.STCY(r.SCRATCH, addr)
+ mc.OGRK(r.SCRATCH, r.SCRATCH, r.SCRATCH2)
+ mc.STC(r.SCRATCH, addr)
# done
else:
byte_index = loc_index.value >> descr.jit_wb_card_page_shift
@@ -589,7 +586,7 @@
addr = l.addr(byte_ofs, loc_base)
mc.LLGC(r.SCRATCH, addr)
mc.OILL(r.SCRATCH, l.imm(byte_val))
- mc.STCY(r.SCRATCH, addr)
+ mc.STC(r.SCRATCH, addr)
#
# patch the beq just above
currpos = mc.currpos()
diff --git a/rpython/jit/backend/zarch/test/test_assembler.py
b/rpython/jit/backend/zarch/test/test_assembler.py
--- a/rpython/jit/backend/zarch/test/test_assembler.py
+++ b/rpython/jit/backend/zarch/test/test_assembler.py
@@ -193,6 +193,16 @@
self.a.mc.BCR(con.ANY, r.r14)
assert run_asm(self.a) == rffi.cast(rffi.ULONG,p) & ~(7)
+ def test_nill(self):
+ self.a.mc.load_imm(r.r2, 1)
+ self.a.mc.load_imm(r.r3, 0x010001)
+ self.a.mc.NILL(r.r3, loc.imm(0xFFFF))
+ self.a.mc.BCR(con.EQ, r.r14) # should not branch
+ self.a.mc.load_imm(r.r2, 0) # should return here
+ self.a.mc.BCR(con.ANY, r.r14)
+ assert run_asm(self.a) == 0
+
+
def test_load_small_int_to_reg(self):
self.a.mc.LGHI(r.r2, loc.imm(123))
self.a.jmpto(r.r14)
_______________________________________________
pypy-commit mailing list
pypy-commit@python.org
https://mail.python.org/mailman/listinfo/pypy-commit
