Author: Richard Plangger <planri...@gmail.com> Branch: s390x-backend Changeset: r82065:785c6853c253 Date: 2016-02-03 22:44 +0100 http://bitbucket.org/pypy/pypy/changeset/785c6853c253/
Log: STC can only tak 12 bits imm, this is wrong (use STCY again), fixed pool issue diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py --- a/rpython/jit/backend/zarch/opassembler.py +++ b/rpython/jit/backend/zarch/opassembler.py @@ -563,13 +563,14 @@ # (index >> card_page_shift) & 7 # 0x80 sets zero flag. will store 0 into all not selected bits mc.RISBGN(r.SCRATCH, loc_index, l.imm(61), l.imm(0x80 | 63), l.imm(64-n)) + #mc.SRAG(r.SCRATCH, loc_index, l.addr(n)) + #mc.NILL(r.SCRATCH, l.imm(0x7)) # set SCRATCH2 to 1 << r1 # invert the bits of tmp_loc - mc.XIHF(tmp_loc, l.imm(0xffffFFFF)) - mc.XILF(tmp_loc, l.imm(0xffffFFFF)) - #mc.LG(r.SCRATCH2, l.pool(self.pool.constant_64_ones)) - #mc.XGR(tmp_loc, r.SCRATCH2) + #mc.XIHF(tmp_loc, l.imm(0xffffFFFF)) + #mc.XILF(tmp_loc, l.imm(0xffffFFFF)) + mc.XG(tmp_loc, l.pool(self.pool.constant_64_ones)) mc.LGHI(r.SCRATCH2, l.imm(1)) mc.SLAG(r.SCRATCH2, r.SCRATCH2, l.addr(0,r.SCRATCH)) @@ -589,7 +590,7 @@ addr = l.addr(byte_ofs, loc_base) mc.LLGC(r.SCRATCH, addr) mc.OILL(r.SCRATCH, l.imm(byte_val)) - mc.STC(r.SCRATCH, addr) + mc.STCY(r.SCRATCH, addr) # # patch the beq just above currpos = mc.currpos() diff --git a/rpython/jit/backend/zarch/pool.py b/rpython/jit/backend/zarch/pool.py --- a/rpython/jit/backend/zarch/pool.py +++ b/rpython/jit/backend/zarch/pool.py @@ -88,6 +88,8 @@ if arg.is_constant(): self.reserve_literal(8, arg) return + elif opnum == rop.COND_CALL_GC_WB_ARRAY: + self.constant_64_ones = 1 # we need constant ones!!! for arg in op.getarglist(): if arg.is_constant(): self.reserve_literal(8, arg) _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit