Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r82256:4d0391440a29
Date: 2016-02-15 11:48 +0100
http://bitbucket.org/pypy/pypy/changeset/4d0391440a29/
Log: sync to remote did not work, fixed more calls to ensure_reg
diff --git a/rpython/jit/backend/zarch/helper/regalloc.py
b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -29,7 +29,6 @@
else:
l1 = self.ensure_reg_or_pool(a1)
self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0, l1]
def prepare_int_mul(self, op):
@@ -43,7 +42,6 @@
else:
l1 = self.ensure_reg_or_pool(a1)
self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0, l1]
def prepare_int_mul_ovf(self, op):
@@ -56,7 +54,6 @@
else:
l1 = self.ensure_reg_or_pool(a1)
lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=False)
- self.free_op_vars()
return [lr, lq, l1]
def generate_div_mod(modulus):
@@ -70,7 +67,6 @@
self.assembler.regalloc_mov(poolloc, lq)
else:
lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=modulus)
- self.free_op_vars()
return [lr, lq, l1]
return f
@@ -81,15 +77,8 @@
a0 = op.getarg(0)
a1 = op.getarg(1)
# sub is not commotative, thus cannot swap operands
- l1 = self.ensure_reg(a1)
- l0 = self.ensure_reg(a0)
- if isinstance(a0, Const):
- loc = self.force_allocate_reg(op)
- self.assembler.mc.LG(loc, l0)
- l0 = loc
- else:
- self.rm.force_result_in_reg(op, a0)
- self.free_op_vars()
+ l1 = self.ensure_reg_or_pool(a1)
+ l0 = self.force_result_in_reg(op, a0)
return [l0, l1]
def prepare_int_logic(self, op):
@@ -97,10 +86,8 @@
a1 = op.getarg(1)
if a0.is_constant():
a0, a1 = a1, a0
- l0 = self.ensure_reg(a0)
- l1 = self.ensure_reg(a1)
- self.force_result_in_reg(op, a0)
- self.free_op_vars()
+ l1 = self.ensure_reg_or_pool(a1)
+ l0 = self.force_result_in_reg(op, a0)
return [l0, l1]
def prepare_int_shift(self, op):
@@ -111,11 +98,10 @@
# in the addr part of the instruction
l1 = addr(a1.getint())
else:
- tmp = self.rm.ensure_reg(a1, force_in_reg=True)
+ tmp = self.rm.ensure_reg(a1)
l1 = addr(0, tmp)
- l0 = self.ensure_reg(a0, force_in_reg=True)
+ l0 = self.ensure_reg(a0)
lr = self.force_allocate_reg(op)
- self.free_op_vars()
return [lr, l0, l1]
def generate_cmp_op(signed=True):
@@ -128,21 +114,14 @@
l1 = imm(a1.getint())
else:
l1 = self.ensure_reg(a1)
- if l0.is_in_pool():
- poolloc = l0
- l0 = self.force_allocate_reg(op)
- self.assembler.mc.LG(l0, poolloc)
res = self.force_allocate_reg_or_cc(op)
- #self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0, l1, res, invert]
return prepare_cmp_op
def prepare_float_cmp_op(self, op):
- l0 = self.ensure_reg(op.getarg(0), force_in_reg=True)
- l1 = self.ensure_reg(op.getarg(1))
+ l0 = self.ensure_reg(op.getarg(0))
+ l1 = self.ensure_reg_or_pool(op.getarg(1))
res = self.force_allocate_reg_or_cc(op)
- self.free_op_vars()
return [l0, l1, res]
def prepare_binary_op(self, op):
@@ -151,7 +130,6 @@
l0 = self.ensure_reg(a0)
l1 = self.ensure_reg(a1)
self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0, l1]
def generate_prepare_float_binary_op(allow_swap=False):
@@ -169,30 +147,24 @@
l0 = newloc
else:
self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0, l1]
return prepare_float_binary_op
def prepare_unary_cmp(self, op):
a0 = op.getarg(0)
- assert not isinstance(a0, ConstInt)
l0 = self.ensure_reg(a0)
self.force_result_in_reg(op, a0)
res = self.force_allocate_reg_or_cc(op)
- self.free_op_vars()
return [l0, res]
def prepare_unary_op(self, op):
a0 = op.getarg(0)
- assert not isinstance(a0, ConstInt)
- l0 = self.ensure_reg(a0, force_in_reg=True)
+ l0 = self.ensure_reg(a0)
res = self.force_result_in_reg(op, a0)
- self.free_op_vars()
return [l0,]
def prepare_same_as(self, op):
a0 = op.getarg(0)
l0 = self.ensure_reg(a0)
res = self.force_allocate_reg(op)
- self.free_op_vars()
return [l0, res]
diff --git a/rpython/jit/backend/zarch/regalloc.py
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -147,8 +147,7 @@
else:
assert box in self.temp_boxes
loc = self.make_sure_var_in_reg(box,
- forbidden_vars=self.temp_boxes,
- selected_reg=selected_reg)
+ forbidden_vars=self.temp_boxes)
return loc
def ensure_reg(self, box):
@@ -163,8 +162,7 @@
else:
assert box in self.temp_boxes
loc = self.make_sure_var_in_reg(box,
- forbidden_vars=self.temp_boxes,
- selected_reg=selected_reg)
+ forbidden_vars=self.temp_boxes)
return loc
def get_scratch_reg(self, selected_reg=None):
@@ -601,7 +599,13 @@
else:
return self.rm.call_result_location(v)
- def ensure_reg(self, box)a:
+ def ensure_reg_or_pool(self, box):
+ if box.type == FLOAT:
+ return self.fprm.ensure_reg_or_pool(box)
+ else:
+ return self.rm.ensure_reg_or_pool(box)
+
+ def ensure_reg(self, box):
if box.type == FLOAT:
return self.fprm.ensure_reg(box)
else:
@@ -609,7 +613,7 @@
def ensure_reg_or_16bit_imm(self, box):
if box.type == FLOAT:
- return self.fprm.ensure_reg(box, True)
+ return self.fprm.ensure_reg(box)
else:
if helper.check_imm(box):
return imm(box.getint())
@@ -625,7 +629,7 @@
def ensure_reg_or_any_imm(self, box):
if box.type == FLOAT:
- return self.fprm.ensure_reg(box):
+ return self.fprm.ensure_reg(box)
else:
if isinstance(box, Const):
return imm(box.getint())
@@ -1107,7 +1111,7 @@
return locs
def prepare_guard_exception(self, op):
- loc = self.ensure_reg(op.getarg(0), force_in_reg=True)
+ loc = self.ensure_reg(op.getarg(0))
if op in self.longevity:
resloc = self.force_allocate_reg(op)
else:
@@ -1116,7 +1120,7 @@
return arglocs
def prepare_guard_is_object(self, op):
- loc_object = self.ensure_reg(op.getarg(0), force_in_reg=True)
+ loc_object = self.ensure_reg(op.getarg(0))
arglocs = self._prepare_guard(op, [loc_object])
return arglocs
@@ -1126,8 +1130,8 @@
prepare_save_exc_class = prepare_save_exception
def prepare_restore_exception(self, op):
- loc0 = self.ensure_reg(op.getarg(0), force_in_reg=True)
- loc1 = self.ensure_reg(op.getarg(1), force_in_reg=True)
+ loc0 = self.ensure_reg(op.getarg(0))
+ loc1 = self.ensure_reg(op.getarg(1))
return [loc0, loc1]
def prepare_copystrcontent(self, op):
@@ -1145,7 +1149,7 @@
must_exist=False, load_loc_odd=False)
src_ofs_loc = self.ensure_reg_or_any_imm(op.getarg(2))
self.rm.temp_boxes.append(src_tmp)
- dst_ptr_loc = self.ensure_reg(op.getarg(1), force_in_reg=True)
+ dst_ptr_loc = self.ensure_reg(op.getarg(1))
dst_ofs_loc = self.ensure_reg_or_any_imm(op.getarg(3))
length_loc = self.ensure_reg_or_any_imm(op.getarg(4))
# no need to spill, we do not call memcpy, but we use s390x's
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