Author: Remi Meier <remi.me...@gmail.com> Branch: fix-longevity Changeset: r82498:d6ea9d88da47 Date: 2016-02-25 13:42 +0100 http://bitbucket.org/pypy/pypy/changeset/d6ea9d88da47/
Log: (plan_rich,remi) small fixes and allow updating the free regs lists diff --git a/rpython/jit/backend/llsupport/regalloc.py b/rpython/jit/backend/llsupport/regalloc.py --- a/rpython/jit/backend/llsupport/regalloc.py +++ b/rpython/jit/backend/llsupport/regalloc.py @@ -310,12 +310,18 @@ return self.free_callee_regs or self.free_caller_regs def allocate_new(self, var): - if self.live_ranges.survives_call(var, self.position): + if self.live_ranges.exists(var) and self.live_ranges.survives_call(var, self.position): # we want a callee save register return self.get_free_register(var, callee=True) else: return self.get_free_register(var, callee=False, target_reg=None) + def update_free_registers(self, regs_in_use): + # XXX: slow? + self._reset_free_regs() + for r in regs_in_use: + self.remove_free_register(r) + def remove_free_register(self, reg): if self.is_callee_lookup[reg.value]: self.free_callee_regs = [fr for fr in self.free_callee_regs if fr is not reg] @@ -335,9 +341,13 @@ return reg in self.free_callee_regs or \ reg in self.free_caller_regs + def _reset_free_regs(self): + self.free_callee_regs = [reg for reg in self.all_regs + if reg not in self.save_around_call_regs] + self.free_caller_regs = self.save_around_call_regs[:] + def __init__(self, live_ranges, frame_manager=None, assembler=None): - self.free_callee_regs = [reg for reg in self.all_regs if reg not in self.save_around_call_regs] - self.free_caller_regs = self.save_around_call_regs[:] + self._reset_free_regs() self.is_callee_lookup = [True] * len(self.all_regs) for reg in self.save_around_call_regs: self.is_callee_lookup[reg.value] = False diff --git a/rpython/jit/backend/llsupport/test/test_regalloc.py b/rpython/jit/backend/llsupport/test/test_regalloc.py --- a/rpython/jit/backend/llsupport/test/test_regalloc.py +++ b/rpython/jit/backend/llsupport/test/test_regalloc.py @@ -23,9 +23,9 @@ class FakeReg(object): def __init__(self, i): - self.index = i + self.value = i def __repr__(self): - return 'r%d' % self.index + return 'r%d' % self.value r0, r1, r2, r3 = [FakeReg(i) for i in range(4)] regs = [r0, r1, r2, r3] diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py --- a/rpython/jit/backend/x86/regalloc.py +++ b/rpython/jit/backend/x86/regalloc.py @@ -266,11 +266,13 @@ else: return self.xrm.make_sure_var_in_reg(var, forbidden_vars) - def _update_bindings(self, locs, inputargs): + def _update_bindings(self, arglocs, inputargs): # XXX this should probably go to llsupport/regalloc.py - used = {} + used = set() i = 0 - for loc in locs: + # manually set the register and frame bindings for + # all inputargs (for a bridge) + for loc in arglocs: if loc is None: # xxx bit kludgy loc = ebp arg = inputargs[i] @@ -278,23 +280,18 @@ if isinstance(loc, RegLoc): if arg.type == FLOAT: self.xrm.reg_bindings[arg] = loc - used[loc] = None + used.add(loc) else: if loc is ebp: self.rm.bindings_to_frame_reg[arg] = None else: self.rm.reg_bindings[arg] = loc - used[loc] = None + used.add(loc) else: self.fm.bind(arg, loc) - self.rm.free_regs = [] - for reg in self.rm.all_regs: - if reg not in used: - self.rm.free_regs.append(reg) - self.xrm.free_regs = [] - for reg in self.xrm.all_regs: - if reg not in used: - self.xrm.free_regs.append(reg) + # + self.rm.update_free_registers(used) + self.xrm.update_free_registers(used) self.possibly_free_vars(list(inputargs)) self.fm.finish_binding() self.rm._check_invariants() _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit