Author: Ronan Lamy <ronan.l...@gmail.com>
Branch: 
Changeset: r84402:338fbdec99c6
Date: 2016-05-12 16:04 +0100
http://bitbucket.org/pypy/pypy/changeset/338fbdec99c6/

Log:    merge heads

diff --git a/pypy/module/_winreg/interp_winreg.py 
b/pypy/module/_winreg/interp_winreg.py
--- a/pypy/module/_winreg/interp_winreg.py
+++ b/pypy/module/_winreg/interp_winreg.py
@@ -16,10 +16,11 @@
 class W_HKEY(W_Root):
     def __init__(self, space, hkey):
         self.hkey = hkey
+        self.space = space
         self.register_finalizer(space)
 
-    def _finalize_(self, space):
-        self.Close(space)
+    def _finalize_(self):
+        self.Close(self.space)
 
     def as_int(self):
         return rffi.cast(rffi.SIZE_T, self.hkey)
diff --git a/rpython/jit/backend/zarch/regalloc.py 
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -312,11 +312,18 @@
             even, odd = r.r2, r.r3
             old_even_var = reverse_mapping.get(even, None)
             old_odd_var = reverse_mapping.get(odd, None)
+
+            # forbid r2 and r3 to be in free regs!
+            self.free_regs = [fr for fr in self.free_regs \
+                              if fr is not even and \
+                                 fr is not odd]
+
             if old_even_var:
                 if old_even_var in forbidden_vars:
                     self._relocate_forbidden_variable(even, old_even_var, 
reverse_mapping,
                                                       forbidden_vars, odd)
                 else:
+                    # old even var is not forbidden, sync it and be done with 
it
                     self._sync_var(old_even_var)
                     del self.reg_bindings[old_even_var]
             if old_odd_var:
@@ -327,9 +334,6 @@
                     self._sync_var(old_odd_var)
                     del self.reg_bindings[old_odd_var]
 
-            self.free_regs = [fr for fr in self.free_regs \
-                              if fr is not even and \
-                                 fr is not odd]
             self.reg_bindings[even_var] = even
             self.reg_bindings[odd_var] = odd
             return even, odd
@@ -342,10 +346,11 @@
             self.assembler.regalloc_mov(reg, candidate)
             self.reg_bindings[var] = candidate
             reverse_mapping[candidate] = var
+            return # we found a location for that forbidden var!
 
         for candidate in r.MANAGED_REGS:
             # move register of var to another register
-            # thus it is not allowed to bei either reg or forbidden_reg
+            # it is NOT allowed to be a reg or forbidden_reg
             if candidate is reg or candidate is forbidden_reg:
                 continue
             # neither can we allow to move it to a register of another 
forbidden variable
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