Author: Richard Plangger <[email protected]>
Branch: zarch-simd-support
Changeset: r87216:28e71ef2f8ec
Date: 2016-09-19 09:11 +0200
http://bitbucket.org/pypy/pypy/changeset/28e71ef2f8ec/
Log: int_is_true fixed
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -329,6 +329,7 @@
'VREPI': ('vri_a', ['\xE7','\x45']),
'VCEQ': ('vrr_b', ['\xE7','\xF8']),
+ 'VCHL': ('vrr_b', ['\xE7','\xF9']),
# pack, merge, shift, ...
'VMRL': ('vrr_c', ['\xE7','\x60'], 'v,v,v,m'),
diff --git a/rpython/jit/backend/zarch/vector_ext.py
b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -186,9 +186,8 @@
size = sizeloc.value
tmploc = regalloc.vrm.get_scratch_reg()
self.mc.VX(tmploc, tmploc, tmploc) # all zero
- self.mc.VNO(tmploc, tmploc, tmploc) # all one
- self.mc.VCEQ(resloc, argloc, tmploc, l.itemsize_to_mask(size), 0b0001)
- flush_vec_cc(self, regalloc, c.VNEI, op.bytesize, resloc)
+ self.mc.VCHL(resloc, argloc, tmploc, l.itemsize_to_mask(size), 0b0001)
+ flush_vec_cc(self, regalloc, c.VEQI, op.bytesize, resloc)
def emit_vec_float_eq(self, op, arglocs, regalloc):
assert isinstance(op, VectorOp)
@@ -574,8 +573,9 @@
prepare_vec_cast_int_to_float = prepare_vec_cast_float_to_int
def prepare_vec_guard_true(self, op):
- self.assembler.guard_success_cc = c.VEQI
+ self.assembler.guard_success_cc = c.EQ
return self._prepare_guard(op)
def prepare_vec_guard_false(self, op):
- self.assembler.guard_success_cc = c.VNEI
+ self.assembler.guard_success_cc = c.NE
+ return self._prepare_guard(op)
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