Author: Ronan Lamy <ronan.l...@gmail.com> Branch: py3k Changeset: r87558:41c743345092 Date: 2016-10-03 20:24 +0100 http://bitbucket.org/pypy/pypy/changeset/41c743345092/
Log: hg merge default diff --git a/rpython/jit/backend/x86/runner.py b/rpython/jit/backend/x86/runner.py --- a/rpython/jit/backend/x86/runner.py +++ b/rpython/jit/backend/x86/runner.py @@ -24,6 +24,8 @@ # can an ISA instruction handle a factor to the offset? load_supported_factors = (1,2,4,8) + HAS_CODEMAP = True + from rpython.jit.backend.x86.arch import JITFRAME_FIXED_SIZE all_reg_indexes = gpr_reg_mgr_cls.all_reg_indexes gen_regs = gpr_reg_mgr_cls.all_regs @@ -148,7 +150,6 @@ CALLEE_SAVE_REGISTERS = [regloc.ebx, regloc.r12, regloc.r13, regloc.r14, regloc.r15] IS_64_BIT = True - HAS_CODEMAP = True class CPU_X86_64_SSE4(CPU_X86_64): vector_extension = True diff --git a/rpython/rlib/rvmprof/test/test_traceback.py b/rpython/rlib/rvmprof/test/test_traceback.py --- a/rpython/rlib/rvmprof/test/test_traceback.py +++ b/rpython/rlib/rvmprof/test/test_traceback.py @@ -1,4 +1,4 @@ -import re +import re, py from rpython.rlib import rvmprof, jit from rpython.rlib.rvmprof import traceback from rpython.translator.interactive import Translation @@ -68,6 +68,10 @@ assert got == [got[0]] * 3 def test_jitted(): + from rpython.jit.backend import detect_cpu + if not detect_cpu.autodetect().startswith('x86'): + py.test.skip("HAS_CODEMAP is only in the x86 jit backend for now") + class MyCode: pass def get_name(mycode): _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit