Author: Maciej Fijalkowski <[email protected]>
Branch: arm64
Changeset: r96417:230e2b6a0bae
Date: 2019-04-05 09:27 +0000
http://bitbucket.org/pypy/pypy/changeset/230e2b6a0bae/
Log: use only first 16 registers and make sure the jitframe_fixed_size
agrees
diff --git a/rpython/jit/backend/aarch64/arch.py
b/rpython/jit/backend/aarch64/arch.py
--- a/rpython/jit/backend/aarch64/arch.py
+++ b/rpython/jit/backend/aarch64/arch.py
@@ -8,5 +8,5 @@
# A jitframe is a jit.backend.llsupport.llmodel.jitframe.JITFRAME
# Stack frame fixed area
# Currently only the force_index
-JITFRAME_FIXED_SIZE = 12 + 8
-# 12 GPR + 8 VFP Regs
+JITFRAME_FIXED_SIZE = 16 + 16
+# 20 GPR + 16 VFP Regs
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -1,7 +1,7 @@
from rpython.jit.backend.aarch64.arch import WORD, JITFRAME_FIXED_SIZE
from rpython.jit.backend.aarch64.codebuilder import InstrBuilder
-#from rpython.jit.backend.arm.locations import imm, StackLocation,
get_fp_offset
+from rpython.jit.backend.arm.locations import imm, StackLocation, get_fp_offset
#from rpython.jit.backend.arm.helper.regalloc import VMEM_imm_size
from rpython.jit.backend.aarch64.opassembler import ResOpAssembler
from rpython.jit.backend.aarch64.regalloc import (Regalloc,
@@ -556,6 +556,10 @@
else:
XXX
+ def new_stack_loc(self, i, tp):
+ base_ofs = self.cpu.get_baseofs_of_frame_field()
+ return StackLocation(i, get_fp_offset(base_ofs, i), tp)
+
def regalloc_mov(self, prev_loc, loc):
"""Moves a value from a previous location to some other location"""
if prev_loc.is_imm():
diff --git a/rpython/jit/backend/aarch64/registers.py
b/rpython/jit/backend/aarch64/registers.py
--- a/rpython/jit/backend/aarch64/registers.py
+++ b/rpython/jit/backend/aarch64/registers.py
@@ -11,7 +11,7 @@
vfpregisters = [VFPRegisterLocation(i) for i in range(32)]
all_vfp_regs = vfpregisters[:16]
-all_regs = registers[:16] + [x19, x20, x21, x22]
+all_regs = registers[:16] #+ [x19, x20, x21, x22]
lr = x30
fp = x29
diff --git a/rpython/jit/backend/aarch64/runner.py
b/rpython/jit/backend/aarch64/runner.py
--- a/rpython/jit/backend/aarch64/runner.py
+++ b/rpython/jit/backend/aarch64/runner.py
@@ -13,6 +13,7 @@
gen_regs = r.all_regs
float_regs = VFPRegisterManager.all_regs
+ from rpython.jit.backend.aarch64.arch import JITFRAME_FIXED_SIZE
IS_64_BIT = True
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