Author: Maciej Fijalkowski <[email protected]>
Branch: arm64
Changeset: r96819:fee018704c07
Date: 2019-06-18 12:11 +0000
http://bitbucket.org/pypy/pypy/changeset/fee018704c07/
Log: enough float support to start running tests
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -6,7 +6,7 @@
from rpython.jit.backend.aarch64.opassembler import ResOpAssembler
from rpython.jit.backend.aarch64.regalloc import (Regalloc, check_imm_arg,
operations as regalloc_operations, guard_operations, comp_operations,
- CoreRegisterManager)
+ CoreRegisterManager, VFPRegisterManager)
from rpython.jit.backend.aarch64 import registers as r
from rpython.jit.backend.arm import conditions as c
from rpython.jit.backend.llsupport import jitframe
@@ -248,9 +248,8 @@
# Push VFP regs
regs = VFPRegisterManager.all_regs
ofs = len(CoreRegisterManager.all_regs) * WORD
- assert check_imm_arg(ofs+base_ofs)
- mc.ADD_ri(r.ip.value, r.fp.value, imm=ofs+base_ofs)
- mc.VSTM(r.ip.value, [vfpr.value for vfpr in regs])
+ for reg in regs:
+ mc.STR_di(reg.value, r.fp.value, ofs + base_ofs + reg.value *
WORD)
def _pop_all_regs_from_jitframe(self, mc, ignored_regs, withfloats,
callee_only=False):
@@ -278,9 +277,8 @@
# Pop VFP regs
regs = VFPRegisterManager.all_regs
ofs = len(CoreRegisterManager.all_regs) * WORD
- assert check_imm_arg(ofs+base_ofs)
- mc.ADD_ri(r.ip.value, r.fp.value, imm=ofs+base_ofs)
- mc.VLDM(r.ip.value, [vfpr.value for vfpr in regs])
+ for reg in regs:
+ mc.LDR_di(reg.value, r.fp.value, ofs + base_ofs + reg.value *
WORD)
def _build_failure_recovery(self, exc, withfloats=False):
mc = InstrBuilder()
@@ -745,11 +743,6 @@
#self.saved_threadlocal_addr = 0 # at offset 0 from location 'sp'
# ^^^XXX save it from register x1 into some place
- if self.cpu.supports_floats:
- XXX
- self.mc.VPUSH([reg.value for reg in r.callee_saved_vfp_registers])
- self.saved_threadlocal_addr += (
- len(r.callee_saved_vfp_registers) * 2 * WORD)
# set fp to point to the JITFRAME, passed in argument 'x0'
self.mc.MOV_rr(r.fp.value, r.x0.value)
@@ -916,13 +909,11 @@
mc = self.mc
if gcrootmap and gcrootmap.is_shadow_stack:
self.gen_footer_shadowstack(gcrootmap, mc)
- if self.cpu.supports_floats:
- XXX
- # mc.VPOP([reg.value for reg in r.callee_saved_vfp_registers])
# pop all callee saved registers
- stack_size = (len(r.callee_saved_registers) + 2) * WORD
+ stack_size = len(r.callee_saved_registers) * WORD
+
for i in range(0, len(r.callee_saved_registers), 2):
mc.LDP_rri(r.callee_saved_registers[i].value,
r.callee_saved_registers[i + 1].value,
@@ -930,6 +921,7 @@
(i + 2) * WORD)
mc.LDP_rr_postindex(r.fp.value, r.lr.value, r.sp.value, stack_size)
+
mc.RET_r(r.lr.value)
def store_reg(self, mc, source, base, ofs=0, helper=None):
diff --git a/rpython/jit/backend/aarch64/codebuilder.py
b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -24,6 +24,12 @@
self.write32((base << 22) | ((offset >> 3) << 10) |
(rn << 5) | rt)
+ def STR_di(self, rt, rn, offset):
+ base = 0b1111110100
+ assert offset & 0x7 == 0
+ assert 0 <= offset < 32768
+ self.write32((base << 22) | ((offset >> 3) << 10) | (rn << 5) | rt)
+
def STP_rr_preindex(self, reg1, reg2, rn, offset):
base = 0b1010100110
assert -512 <= offset < 512
@@ -110,6 +116,12 @@
assert immed & 0x7 == 0
self.write32((base << 22) | (immed >> 3 << 10) | (rn << 5) | rt)
+ def LDR_di(self, rt, rn, offset):
+ assert offset & 0x7 == 0
+ assert 0 <= offset < 32768
+ base = 0b1111110101
+ self.write32((base << 22) | (offset >> 3 << 10) | (rn << 5) | rt)
+
def LDRB_ri(self, rt, rn, immed):
base = 0b0011100101
assert 0 <= immed <= 1<<12
@@ -340,6 +352,8 @@
def get_max_size_of_gen_load_int(self):
return 4
+ # -------------------------------------------
+
class OverwritingBuilder(AbstractAarch64Builder):
def __init__(self, cb, start, size):
diff --git a/rpython/jit/backend/aarch64/registers.py
b/rpython/jit/backend/aarch64/registers.py
--- a/rpython/jit/backend/aarch64/registers.py
+++ b/rpython/jit/backend/aarch64/registers.py
@@ -10,7 +10,7 @@
x21, x22, x23, x24, x25, x26, x27, x28, x29, x30] = registers
vfpregisters = [VFPRegisterLocation(i) for i in range(32)]
-all_vfp_regs = vfpregisters[:16]
+all_vfp_regs = vfpregisters[:8]
all_regs = registers[:16] #+ [x19, x20, x21, x22]
lr = x30
@@ -22,6 +22,7 @@
ip0 = x16
callee_saved_registers = [] # x19, x20, x21, x22]
+vfp_argument_regs = caller_vfp_resp = all_vfp_regs[:8]
argument_regs = [x0, x1, x2, x3, x4, x5, x6, x7]
caller_resp = argument_regs + [x8, x9, x10, x11, x12, x13, x14, x15]
diff --git a/rpython/jit/backend/aarch64/runner.py
b/rpython/jit/backend/aarch64/runner.py
--- a/rpython/jit/backend/aarch64/runner.py
+++ b/rpython/jit/backend/aarch64/runner.py
@@ -12,6 +12,7 @@
all_reg_indexes = range(len(r.all_regs))
gen_regs = r.all_regs
float_regs = VFPRegisterManager.all_regs
+ supports_floats = True
from rpython.jit.backend.aarch64.arch import JITFRAME_FIXED_SIZE
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