Author: Armin Rigo <[email protected]>
Branch: arm64
Changeset: r96921:2486e872ccdf
Date: 2019-07-02 17:10 +0200
http://bitbucket.org/pypy/pypy/changeset/2486e872ccdf/
Log: fix the next bug
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -752,7 +752,8 @@
shiftsize)
self.mc.ADD_rr(r.x1.value, r.x1.value, r.x0.value)
if force_realignment:
- self.mc.MVN_rr_shifted(r.ip0.value, r.ip0.value, WORD - 1)
+ # -WORD = 0xfffffffffffffff8
+ self.mc.gen_load_int(r.ip0.value, -WORD)
self.mc.AND_rr(r.x1.value, r.x1.value, r.ip0.value)
# now x1 contains the total size in bytes, rounded up to a multiple
# of WORD, plus nursery_free_adr
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