Mark Dickinson added the comment:
An implementation note: IEEE 754-2008 leaves it to the implementation to decide
whether FMA operations like:
0 * inf + nan
and
inf * 0 + nan
(where nan represents a quiet NaN and the inf and 0 can have arbitrary signs)
signal the invalid operation FPE or not. (Ref: 7.2(c) in IEEE 754-2008.)
I'd suggest that in this case we follow what Intel does in its x64 chips with
FMA3 support.(according to ). If I'm reading the table in section 2.3 of the
Intel Advanced Vector Extensions Programming Reference correctly, Intel does
*not* signal the invalid operation FPE in this case. That is, we're following
the usual rule of quiet NaN in => quiet NaN out with no exception. This does
unfortunately conflict with the IBM decimal specification and Python's decimal
module, where these operations *do* set the "invalid" flag (see the spec, and
test fmax0809 in the decimal test set).
----------
nosy: +skrah
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