On Jul 23, 1:03 pm, [EMAIL PROTECTED] (c d saunter) wrote: > How much of VHDL are you looking to parse? Are you just looking at files > intended for synthesis, or at simulation/testbench files as well?
As a start I want to parse VHDL which is going to be synthesised, and I am limiting myself to the entities and the structural component placement. I will drop the processes and the concurrent assignments even if that will mask important information. It is a design viewer tool, not a design tool that I am writing. Xilinx ISE do give me the opportunity to browse my synthesised netlist, but there is simply too much information. Later the app can be extended with more functionality, depends on my success with the initial problems that I have. > If I started again I'd use pyparsing:http://pyparsing.wikispaces.com/ > > Looks like someone is already there in > part:http://pyparsing.wikispaces.com/message/view/home/103973 I also got a pointer to SimpleParse and now try to translate the parts of the VHDL BNF that I need into a definition that SimpleParse can understand. But looking at the BNF it is clear that VHDL is no easy language to parse, just as it is no easy language to do structural design in. -- Svenn -- http://mail.python.org/mailman/listinfo/python-list
