tuxlover wrote: > Hello everyone > > I have to write a verilog parser in python for a class project. I was > wondering if all you folks could advise me on choosing the right python > parser module. I am not comfortable with lex/yacc and as a result find > myself strugging with any module which use lex/yacc syntax/philosophy. > pyparser looks good to me, but before I dive into it, I would really > appreciate feedback from members of this group
A Verilog parser has been written using pyparsing at least once before, so I imagine that it shouldn't be too difficult to do so again. Of course, if you just need *a* Verilog parser, not necessarily one written by you, you could just email the guy who wrote it and ask him for a copy. Grep http://pyparsing.sourceforge.net/ for "Verilog". -- Robert Kern [EMAIL PROTECTED] "In the fields of hell where the grass grows high Are the graves of dreams allowed to die." -- Richard Harter -- http://mail.python.org/mailman/listinfo/python-list