On Sat, 22 Apr 2023, Bernhard Beschow wrote:
The VIA south bridge allows the legacy IDE interrupts to be routed to four
different ISA interrupts. This can be configured through the 0x4a register in
the PCI configuration space of the ISA function. The default routing matches
the legacy ISA IRQs, that is 14 and 15.
On VT8231 0x4a is PCI Master Arbitration Control, IDE interrupt Routing is
0x4c and only documents 14/15 as valid values. Not sure any guest would
actually change this or 0x4a and if that could cause problems but you may
need to handle this somehow. (Apart from testing with MorphOS with -kernel
you should really be testing with pegasos2.rom with MorphOS and Linux,
e.g. Debian 8.11 netinstall iso is known to boot.)
Regards,
BALATON Zoltan
Implement this missing piece of the VIA south bridge.
Signed-off-by: Bernhard Beschow <shen...@gmail.com>
---
hw/ide/via.c | 6 ++++--
hw/isa/vt82c686.c | 17 +++++++++++++++++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 177baea9a7..0caae52276 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -31,6 +31,7 @@
#include "sysemu/dma.h"
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
+#include "hw/irq.h"
#include "trace.h"
static uint64_t bmdma_read(void *opaque, hwaddr addr,
@@ -104,7 +105,8 @@ static void bmdma_setup_bar(PCIIDEState *d)
static void via_ide_set_irq(void *opaque, int n, int level)
{
- PCIDevice *d = PCI_DEVICE(opaque);
+ PCIIDEState *s = opaque;
+ PCIDevice *d = PCI_DEVICE(s);
if (level) {
d->config[0x70 + n * 8] |= 0x80;
@@ -112,7 +114,7 @@ static void via_ide_set_irq(void *opaque, int n, int level)
d->config[0x70 + n * 8] &= ~0x80;
}
- via_isa_set_irq(pci_get_function_0(d), 14 + n, level);
+ qemu_set_irq(s->isa_irq[n], level);
}
static void via_ide_reset(DeviceState *dev)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index ca89119ce0..c7e29bb46a 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -568,9 +568,19 @@ static const VMStateDescription vmstate_via = {
}
};
+static void via_isa_set_ide_irq(void *opaque, int n, int level)
+{
+ static const uint8_t irqs[] = { 14, 15, 10, 11 };
+ ViaISAState *s = opaque;
+ uint8_t irq = irqs[(s->dev.config[0x4a] >> (n * 2)) & 0x3];
+
+ qemu_set_irq(s->isa_irqs_in[irq], level);
+}
+
static void via_isa_init(Object *obj)
{
ViaISAState *s = VIA_ISA(obj);
+ DeviceState *dev = DEVICE(s);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE);
@@ -578,6 +588,8 @@ static void via_isa_init(Object *obj)
object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI);
object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97);
object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97);
+
+ qdev_init_gpio_in_named(dev, via_isa_set_ide_irq, "ide",
ARRAY_SIZE(s->ide.isa_irq));
}
static const TypeInfo via_isa_info = {
@@ -692,6 +704,10 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
return;
}
+ for (i = 0; i < 2; i++) {
+ qdev_connect_gpio_out(DEVICE(&s->ide), i,
+ qdev_get_gpio_in_named(DEVICE(s), "ide", i));
+ }
/* Functions 2-3: USB Ports */
for (i = 0; i < ARRAY_SIZE(s->uhci); i++) {
@@ -814,6 +830,7 @@ static void vt8231_isa_reset(DeviceState *dev)
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
+ pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */
pci_conf[0x67] = 0x08; /* Fast IR Config */
pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */
