Instantiate TYPE_ICH9_LPC_DEVICE in TYPE_ICH9_SOUTHBRIDGE.
Expose the SMM property so the Q35 machine can disable it
(depending on the accelerator used).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
include/hw/southbridge/ich9.h | 4 ----
hw/i386/pc_q35.c | 20 ++++++--------------
hw/isa/ich9_lpc.c | 3 +++
hw/southbridge/ich9.c | 15 +++++++++++++++
hw/i386/Kconfig | 1 -
hw/southbridge/Kconfig | 1 +
6 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h
index d6c3b5ece3..a8da4a8665 100644
--- a/include/hw/southbridge/ich9.h
+++ b/include/hw/southbridge/ich9.h
@@ -16,10 +16,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE)
#define ICH9_PCIE_DEV 28
#define ICH9_PCIE_FUNC_MAX 6
-/* D31:F1 LPC controller */
-#define ICH9_LPC_DEV 31
-#define ICH9_LPC_FUNC 0
-
#define ICH9_GPIO_GSI "gsi"
#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 14df9e910b..31ab0ae77b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -50,7 +50,6 @@
#include "hw/ide/ahci-pci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
-#include "hw/isa/ich9_lpc.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/numa.h"
@@ -67,9 +66,7 @@ static void pc_q35_init(MachineState *machine)
X86MachineState *x86ms = X86_MACHINE(machine);
Object *phb;
DeviceState *ich9;
- PCIDevice *lpc;
Object *lpc_obj;
- DeviceState *lpc_dev;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
@@ -168,24 +165,19 @@ static void pc_q35_init(MachineState *machine)
object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9));
object_property_set_link(OBJECT(ich9), "mch-pcie-bus",
OBJECT(pcms->pcibus), &error_abort);
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ qdev_connect_gpio_out_named(ich9, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
+ }
qdev_prop_set_bit(ich9, "d2p-enabled", false);
+ qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86ms));
qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled);
qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled);
/* Should we create 6 UHCI according to ich9 spec? */
qdev_prop_set_uint8(ich9, "ehci-count", machine_usb(machine) ? 1 : 0);
qdev_realize_and_unref(ich9, NULL, &error_fatal);
- /* create ISA bus */
- lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
- TYPE_ICH9_LPC_DEVICE);
- lpc_obj = OBJECT(lpc);
- lpc_dev = DEVICE(lpc);
- qdev_prop_set_bit(lpc_dev, "smm-enabled",
- x86_machine_is_smm_enabled(x86ms));
- for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
- }
- pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal);
+ /* ISA bus */
+ lpc_obj = object_resolve_path_component(OBJECT(ich9), "lpc");
x86ms->rtc = ISA_DEVICE(object_resolve_path_component(lpc_obj, "rtc"));
diff --git a/hw/isa/ich9_lpc.c b/hw/isa/ich9_lpc.c
index 17d4a95bd2..2339f66e0f 100644
--- a/hw/isa/ich9_lpc.c
+++ b/hw/isa/ich9_lpc.c
@@ -54,6 +54,9 @@
#include "hw/acpi/acpi_aml_interface.h"
#include "trace.h"
+#define ICH9_LPC_DEV 31
+#define ICH9_LPC_FUNC 0
+
#define ICH9_A2_LPC_REVISION 0x2
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c
index f05012959d..521925b462 100644
--- a/hw/southbridge/ich9.c
+++ b/hw/southbridge/ich9.c
@@ -13,6 +13,7 @@
#include "hw/southbridge/ich9.h"
#include "hw/pci/pci.h"
#include "hw/pci-bridge/ich9_dmi.h"
+#include "hw/isa/ich9_lpc.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide/ide-dev.h"
#include "hw/i2c/ich9_smbus.h"
@@ -21,6 +22,7 @@
#include "hw/usb/hcd-uhci.h"
#define ICH9_D2P_DEVFN PCI_DEVFN(30, 0)
+#define ICH9_LPC_DEVFN PCI_DEVFN(31, 0)
#define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2)
#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3)
#define ICH9_EHCI_FUNC 7
@@ -34,6 +36,7 @@ struct ICH9State {
I82801b11Bridge d2p;
AHCIPCIState sata0;
+ ICH9LPCState lpc;
ICH9SMBState smb;
EHCIPCIState ehci[EHCI_PER_FN];
UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN];
@@ -57,6 +60,14 @@ static Property ich9_props[] = {
static void ich9_init(Object *obj)
{
+ ICH9State *s = ICH9_SOUTHBRIDGE(obj);
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE);
+ qdev_pass_gpios(DEVICE(&s->lpc), DEVICE(s), ICH9_GPIO_GSI);
+ qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN);
+ qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true);
+ object_property_add_alias(obj, "smm-enabled",
+ OBJECT(&s->lpc), "smm-enabled");
}
static bool ich9_realize_d2p(ICH9State *s, Error **errp)
@@ -163,6 +174,10 @@ static void ich9_realize(DeviceState *dev, Error **errp)
return;
}
+ if (!qdev_realize(DEVICE(&s->lpc), BUS(s->pci_bus), errp)) {
+ return;
+ }
+
if (s->sata_enabled && !ich9_realize_sata(s, errp)) {
return;
}
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 226d7f6916..eccc834e49 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -100,7 +100,6 @@ config Q35
select PC_ACPI
select PCI_EXPRESS_Q35
select ICH9
- select LPC_ICH9
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig
index 31eb125bf7..8ce62b703c 100644
--- a/hw/southbridge/Kconfig
+++ b/hw/southbridge/Kconfig
@@ -8,3 +8,4 @@ config ICH9
select ACPI_ICH9
imply USB_EHCI_PCI
imply USB_UHCI
+ select LPC_ICH9
--
2.41.0
