From: Minwoo Im <minwoo...@samsung.com>
Secondary controller list for virtualization has been managed by
Identify Secondary Controller List data structure with NvmeSecCtrlList
where up to 127 secondary controller entries can be managed. The
problem hasn't arisen so far because NVME_MAX_VFS has been 127.
This patch separated identify data itself from the actual secondary
controller list managed by controller to support more than 127 secondary
controllers with the following patch. This patch reused
NvmeSecCtrlEntry structure to manage all the possible secondary
controllers, and copy entries to identify data structure when the
command comes in.
Signed-off-by: Minwoo Im <minwoo...@samsung.com>
---
hw/nvme/ctrl.c | 21 ++++++++++-----------
hw/nvme/nvme.h | 14 ++++++++------
hw/nvme/subsys.c | 8 ++++----
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 18672f66193f..7cf1e8e384b7 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -219,7 +219,6 @@
#define NVME_TEMPERATURE_CRITICAL 0x175
#define NVME_NUM_FW_SLOTS 1
#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
-#define NVME_MAX_VFS 127
#define NVME_VF_RES_GRANULARITY 1
#define NVME_VF_OFFSET 0x1
#define NVME_VF_STRIDE 1
@@ -5480,14 +5479,14 @@ static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl
*n, NvmeRequest *req)
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint16_t pri_ctrl_id = le16_to_cpu(n->pri_ctrl_cap.cntlid);
uint16_t min_id = le16_to_cpu(c->ctrlid);
- uint8_t num_sec_ctrl = n->sec_ctrl_list.numcntl;
+ uint8_t num_sec_ctrl = n->nr_sec_ctrls;
NvmeSecCtrlList list = {0};
uint8_t i;
for (i = 0; i < num_sec_ctrl; i++) {
- if (n->sec_ctrl_list.sec[i].scid >= min_id) {
- list.numcntl = num_sec_ctrl - i;
- memcpy(&list.sec, n->sec_ctrl_list.sec + i,
+ if (n->sec_ctrl_list[i].scid >= min_id) {
+ list.numcntl = MIN(num_sec_ctrl - i, 127);
+ memcpy(&list.sec, n->sec_ctrl_list + i,
list.numcntl * sizeof(NvmeSecCtrlEntry));
break;
}
@@ -7144,8 +7143,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType
rst)
if (n->params.sriov_max_vfs) {
if (!pci_is_vf(pci_dev)) {
- for (i = 0; i < n->sec_ctrl_list.numcntl; i++) {
- sctrl = &n->sec_ctrl_list.sec[i];
+ for (i = 0; i < n->nr_sec_ctrls; i++) {
+ sctrl = &n->sec_ctrl_list[i];
nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
}
}
@@ -7934,7 +7933,7 @@ static bool nvme_check_params(NvmeCtrl *n, Error **errp)
static void nvme_init_state(NvmeCtrl *n)
{
NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
PCIDevice *pci = PCI_DEVICE(n);
uint8_t max_vfs;
@@ -7959,9 +7958,9 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
QTAILQ_INIT(&n->aer_queue);
- list->numcntl = max_vfs;
+ n->nr_sec_ctrls = max_vfs;
for (i = 0; i < max_vfs; i++) {
- sctrl = &list->sec[i];
+ sctrl = &list[i];
sctrl->pcid = cpu_to_le16(n->cntlid);
sctrl->vfn = cpu_to_le16(i + 1);
}
@@ -8534,7 +8533,7 @@ static void nvme_sriov_post_write_config(PCIDevice *dev,
uint16_t old_num_vfs)
int i;
for (i = pcie_sriov_num_vfs(dev); i < old_num_vfs; i++) {
- sctrl = &n->sec_ctrl_list.sec[i];
+ sctrl = &n->sec_ctrl_list[i];
nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false);
}
}
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index bed8191bd5fd..485b42c104ea 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -26,6 +26,7 @@
#define NVME_MAX_CONTROLLERS 256
#define NVME_MAX_NAMESPACES 256
+#define NVME_MAX_VFS 127
#define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000)
#define NVME_FDP_MAX_EVENTS 63
#define NVME_FDP_MAXPIDS 128
@@ -612,7 +613,8 @@ typedef struct NvmeCtrl {
} features;
NvmePriCtrlCap pri_ctrl_cap;
- NvmeSecCtrlList sec_ctrl_list;
+ uint32_t nr_sec_ctrls;
+ NvmeSecCtrlEntry sec_ctrl_list[NVME_MAX_VFS];
struct {
uint16_t vqrfap;
uint16_t virfap;
@@ -662,7 +664,7 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n)
NvmeCtrl *pf = NVME(pcie_sriov_get_pf(pci_dev));
if (pci_is_vf(pci_dev)) {
- return &pf->sec_ctrl_list.sec[pcie_sriov_vf_number(pci_dev)];
+ return &pf->sec_ctrl_list[pcie_sriov_vf_number(pci_dev)];
}
return NULL;
@@ -671,12 +673,12 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n)
static inline NvmeSecCtrlEntry *nvme_sctrl_for_cntlid(NvmeCtrl *n,
uint16_t cntlid)
{
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
uint8_t i;
- for (i = 0; i < list->numcntl; i++) {
- if (le16_to_cpu(list->sec[i].scid) == cntlid) {
- return &list->sec[i];
+ for (i = 0; i < n->nr_sec_ctrls; i++) {
+ if (le16_to_cpu(list[i].scid) == cntlid) {
+ return &list[i];
}
}
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
index d30bb8bfd5b4..561ed04a5317 100644
--- a/hw/nvme/subsys.c
+++ b/hw/nvme/subsys.c
@@ -17,13 +17,13 @@
static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num)
{
NvmeSubsystem *subsys = n->subsys;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
int i, cnt = 0;
for (i = start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) {
if (!subsys->ctrls[i]) {
- sctrl = &list->sec[cnt];
+ sctrl = &list[cnt];
sctrl->scid = cpu_to_le16(i);
subsys->ctrls[i] = SUBSYS_SLOT_RSVD;
cnt++;
@@ -36,12 +36,12 @@ static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int
start, int num)
static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n)
{
NvmeSubsystem *subsys = n->subsys;
- NvmeSecCtrlList *list = &n->sec_ctrl_list;
+ NvmeSecCtrlEntry *list = n->sec_ctrl_list;
NvmeSecCtrlEntry *sctrl;
int i, cntlid;
for (i = 0; i < n->params.sriov_max_vfs; i++) {
- sctrl = &list->sec[i];
+ sctrl = &list[i];
cntlid = le16_to_cpu(sctrl->scid);
if (cntlid) {
--
2.34.1
