Add two gpio outputs to control the uart resets. Signed-off-by: Damien Hedde <damien.he...@greensocs.com> --- hw/misc/zynq_slcr.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 6fcdbce4f0..b6c9a281c2 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -97,6 +97,10 @@ REG32(SPI_RST_CTRL, 0x21c) REG32(CAN_RST_CTRL, 0x220) REG32(I2C_RST_CTRL, 0x224) REG32(UART_RST_CTRL, 0x228) + FIELD(UART_RST_CTRL, UART0_CPU1X_RST, 0, 1) + FIELD(UART_RST_CTRL, UART1_CPU1X_RST, 1, 1) + FIELD(UART_RST_CTRL, UART0_REF_RST, 2, 1) + FIELD(UART_RST_CTRL, UART1_REF_RST, 3, 1) REG32(GPIO_RST_CTRL, 0x22c) REG32(LQSPI_RST_CTRL, 0x230) REG32(SMC_RST_CTRL, 0x234) @@ -190,8 +194,14 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + qemu_irq uart0_rst; + qemu_irq uart1_rst; } ZynqSLCRState; +#define ZYNQ_SLCR_REGFIELD_TO_OUT(state, irq, reg, field) \ + qemu_set_irq((state)->irq, ARRAY_FIELD_EX32((state)->regs, reg, field) != 0) + static void zynq_slcr_reset_init(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -293,6 +303,24 @@ static void zynq_slcr_reset_init(Object *obj) s->regs[R_DDRIOB + 12] = 0x00000021; } +static void zynq_slcr_compute_uart_reset(ZynqSLCRState *s) +{ + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart0_rst, UART_RST_CTRL, UART0_REF_RST); + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart1_rst, UART_RST_CTRL, UART1_REF_RST); +} + +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s = ZYNQ_SLCR(obj); + ZynqSLCRClass *zc = ZYNQ_SLCR_GET_CLASS(obj); + + if (zc->parent_reset_phases.hold) { + zc->parent_reset_phases.hold(obj); + } + + zynq_slcr_compute_uart_reset(s); +} + static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { switch (offset) { @@ -432,6 +460,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_UART_RST_CTRL: + zynq_slcr_compute_uart_reset(s); + break; } } @@ -448,6 +479,9 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_gpio_out_named(DEVICE(obj), &s->uart0_rst, "uart0_rst", 1); + qdev_init_gpio_out_named(DEVICE(obj), &s->uart1_rst, "uart1_rst", 1); } static const VMStateDescription vmstate_zynq_slcr = { @@ -470,7 +504,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void *data) resettable_class_set_parent_reset_phases(rc, zynq_slcr_reset_init, - NULL, + zynq_slcr_reset_hold, NULL, &zc->parent_reset_phases); } -- 2.22.0