This patch sets CMBS bit in controller capabilities register when user configures NVMe driver with CMB support, so capabilites are correctly reported to guest OS.
Signed-off-by: Andrzej Jakowski <andrzej.jakow...@linux.intel.com> Reviewed-by: Klaus Jensen <k.jen...@samsung.com> --- hw/block/nvme.c | 2 ++ include/block/nvme.h | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index a21eeca2fb..f0b45704be 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1449,6 +1449,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) n->bar.intmc = n->bar.intms = 0; if (n->cmb_size_mb) { + /* Contoller capabilities */ + NVME_CAP_SET_CMBS(n->bar.cap, 1); NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); diff --git a/include/block/nvme.h b/include/block/nvme.h index 5525c8e343..b48349dbd0 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -35,6 +35,7 @@ enum NvmeCapShift { CAP_MPSMIN_SHIFT = 48, CAP_MPSMAX_SHIFT = 52, CAP_PMR_SHIFT = 56, + CAP_CMB_SHIFT = 57, }; enum NvmeCapMask { @@ -48,6 +49,7 @@ enum NvmeCapMask { CAP_MPSMIN_MASK = 0xf, CAP_MPSMAX_MASK = 0xf, CAP_PMR_MASK = 0x1, + CAP_CMB_MASK = 0x1, }; #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -78,8 +80,10 @@ enum NvmeCapMask { << CAP_MPSMIN_SHIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ << CAP_MPSMAX_SHIFT) -#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ +#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK) \ << CAP_PMR_SHIFT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK) \ + << CAP_CMB_SHIFT) enum NvmeCcShift { CC_EN_SHIFT = 0, -- 2.21.1