On Mon, 19 Jul 2021 at 23:46, Klaus Jensen <i...@irrelevant.dk> wrote: > > From: Klaus Jensen <k.jen...@samsung.com> > > The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to > make up the 64 bit logical PMRMSC register. > > Make it so. > > Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
> diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index 2f0524e12a36..28299c6f3764 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -5916,11 +5916,12 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr > offset, uint64_t data, > return; > } > > - n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff); > + n->bar.pmrmscl = data & 0xffffffff; This mask is unnecessary because pmrmscl is uint32_t. > n->pmr.cmse = false; > > - if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) { > - hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT; > + if (NVME_PMRMSCL_CMSE(n->bar.pmrmscl)) { > + hwaddr cba = n->bar.pmrmscu | pmrmscu still needs to be shifted left by 32 here. > + (NVME_PMRMSCL_CBA(n->bar.pmrmscl) << PMRMSCL_CBA_SHIFT); > if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { > NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1); > return; > @@ -5936,7 +5937,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, > uint64_t data, > return; > } > > - n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32); > + n->bar.pmrmscu = data & 0xffffffff; Mask not required. > return; > default: > NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, > -- thanks -- PMM