According to NVM Express v1.4, Section 5.21.1.11 (Asynchronous Event
Configuration), introduce bit 0 ~ bit 5.
Signed-off-by: zhenwei pi <pizhen...@bytedance.com>
---
include/block/nvme.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 3737351cc8..d92912f9ad 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -1122,7 +1122,13 @@ typedef struct NvmeIdCtrlNvm {
} NvmeIdCtrlNvm;
enum NvmeIdCtrlOaes {
- NVME_OAES_NS_ATTR = 1 << 8,
+ NVME_OAES_SMART_SPARE = NVME_SMART_SPARE,
+ NVME_OAES_SMART_TEMPERATURE = NVME_SMART_TEMPERATURE,
+ NVME_OAES_SMART_RELIABILITY = NVME_SMART_RELIABILITY,
+ NVME_OAES_SMART_MEDIA_READ_ONLY = NVME_SMART_MEDIA_READ_ONLY,
+ NVME_OAES_SMART_FAILED_VOLATILE_MEDIA = NVME_SMART_FAILED_VOLATILE_MEDIA,
+ NVME_OAES_SMART_PMR_UNRELIABLE = NVME_SMART_PMR_UNRELIABLE,
+ NVME_OAES_NS_ATTR = 1 << 8,
};
enum NvmeIdCtrlCtratt {
--
2.20.1
