Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 709e4407add7acacc593cb6cdac026558c9a8fb6
https://github.com/qemu/qemu/commit/709e4407add7acacc593cb6cdac026558c9a8fb6
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct MPU trace handling of write vs execute
Correct off-by-one bug in the PSMAv7 MPU tracing where it would print
a write access as "reading", an insn fetch as "writing", and a read
access as "execute".
Since we have an MMUAccessType enum now, we can make the code clearer
in the process by using that rather than the raw 0/1/2 values.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Message-id: 1500906792-18010-1-git-send-email-peter.mayd...@linaro.org
Commit: 38aaa60ca464b48e6feef346709e97335d01b289
https://github.com/qemu/qemu/commit/38aaa60ca464b48e6feef346709e97335d01b289
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't do MPU lookups for addresses in M profile PPB region
The M profile PMSAv7 specification says that if the address being looked
up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use
the MPU regions but always use the default memory map. Implement this
(we were previously behaving like an R profile PMSAv7, which does not
special case this).
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1501153150-19984-2-git-send-email-peter.mayd...@linaro.org
Commit: bf446a11dfb17ae7d8ed2b61a2444804eb458075
https://github.com/qemu/qemu/commit/bf446a11dfb17ae7d8ed2b61a2444804eb458075
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't allow guest to make System space executable for M profile
For an M profile v7PMSA, the system space (0xe0000000 - 0xffffffff) can
never be executable, even if the guest tries to set the MPU registers
up that way. Enforce this restriction.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1501153150-19984-3-git-send-email-peter.mayd...@linaro.org
Commit: 8531eb4f614a60e6582d4832b15eee09f7d27874
https://github.com/qemu/qemu/commit/8531eb4f614a60e6582d4832b15eee09f7d27874
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Almost all of the PMSAv7 state is in the pmsav7 substruct of
the ARM CPU state structure. The exception is the region
number register, which is in cp15.c6_rgnr. This exception
is a bit odd for M profile, which otherwise generally does
not store state in the cp15 substruct.
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1501153150-19984-4-git-send-email-peter.mayd...@linaro.org
Commit: 69ceea64bf565559a2b865ffb2a097d2caab805b
https://github.com/qemu/qemu/commit/69ceea64bf565559a2b865ffb2a097d2caab805b
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
When the PMSAv7 implementation was originally added it was for R profile
CPUs only, and reset was handled using the cpreg .resetfn hooks.
Unfortunately for M profile cores this doesn't work, because they do
not register any cpregs. Move the reset handling into arm_cpu_reset(),
where it will work for both R profile and M profile cores.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1501153150-19984-5-git-send-email-peter.mayd...@linaro.org
Commit: f1a4694078f1b43cb2f72a1ec81b1c635d8793d1
https://github.com/qemu/qemu/commit/f1a4694078f1b43cb2f72a1ec81b1c635d8793d1
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Migrate MPU_RNR register state for M profile cores
The PMSAv7 region number register is migrated for R profile
cores using the cpreg scheme, but M profile doesn't use
cpregs, and so we weren't migrating the MPU_RNR register state
at all. Fix that by adding a migration subsection for the
M profile case.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1501153150-19984-6-git-send-email-peter.mayd...@linaro.org
Commit: 89cbc3778a3d61761e2231e740269218c9a8a41d
https://github.com/qemu/qemu/commit/89cbc3778a3d61761e2231e740269218c9a8a41d
Author: Philippe Mathieu-Daudé <f4...@amsat.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M hw/misc/mps2-scc.c
Log Message:
-----------
hw/mps2_scc: fix incorrect properties
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170729234930.725-1-f4...@amsat.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 5619c179057e24195ff19c8fe6d6a6cbcb16ed28
https://github.com/qemu/qemu/commit/5619c179057e24195ff19c8fe6d6a6cbcb16ed28
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-07-31 (Mon, 31 Jul 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M hw/misc/mps2-scc.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170731'
into staging
target-arm queue:
* fix broken properties on MPS2 SCC device
* fix MPU trace handling of write vs exec
* fix MPU M profile bugs:
- not handling system space or PPB region correctly
- not resetting state
- not migrating MPU_RNR
# gpg: Signature made Mon 31 Jul 2017 13:21:40 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg: aka "Peter Maydell <pmayd...@gmail.com>"
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170731:
hw/mps2_scc: fix incorrect properties
target/arm: Migrate MPU_RNR register state for M profile cores
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
target/arm: Don't allow guest to make System space executable for M profile
target/arm: Don't do MPU lookups for addresses in M profile PPB region
target/arm: Correct MPU trace handling of write vs execute
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/bdf211f88411...5619c179057e
