Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 5f486f9713aae854e4bc0a0ce8c5a11a9f6f15c1
https://github.com/qemu/qemu/commit/5f486f9713aae854e4bc0a0ce8c5a11a9f6f15c1
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/armv7m.c
Log Message:
-----------
armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170905131149.10669-2-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e2ff1215b0b150929ff45ff9b14186110629d8bf
https://github.com/qemu/qemu/commit/e2ff1215b0b150929ff45ff9b14186110629d8bf
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/armv7m.c
Log Message:
-----------
armv7m: Convert armv7m.memory to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170905131149.10669-3-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 9ea26c70498cde1887746222c3cada968e46ec23
https://github.com/qemu/qemu/commit/9ea26c70498cde1887746222c3cada968e46ec23
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/arm_gicv3_its_kvm.c
Log Message:
-----------
gicv3: Convert to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Message-id: 20170905131149.10669-4-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c3acfa0129f9ee334936e157bfd19d8fa702b02c
https://github.com/qemu/qemu/commit/c3acfa0129f9ee334936e157bfd19d8fa702b02c
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/xlnx-zynqmp.c
Log Message:
-----------
xlnx_zynqmp: Convert to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170905131149.10669-5-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 26cfb11f40becd6c480027096cbb866ec5e3d3d5
https://github.com/qemu/qemu/commit/26cfb11f40becd6c480027096cbb866ec5e3d3d5
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/net/xilinx_axienet.c
Log Message:
-----------
xilinx_axienet: Convert to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170905131149.10669-6-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 39d3d8081047189614194a4bf2ebac2692738417
https://github.com/qemu/qemu/commit/39d3d8081047189614194a4bf2ebac2692738417
Author: Fam Zheng <f...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/dma/xilinx_axidma.c
Log Message:
-----------
xilinx_axidma: Convert to DEFINE_PROP_LINK
Signed-off-by: Fam Zheng <f...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20170905131149.10669-7-f...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: dc89a180caf143a5d596d3f2f776d13be83a687d
https://github.com/qemu/qemu/commit/dc89a180caf143a5d596d3f2f776d13be83a687d
Author: Thomas Huth <th...@redhat.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/allwinner-a10.c
M scripts/device-crash-test
Log Message:
-----------
hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable =
false
QEMU currently exits unexpectedly when the user accidentially
tries to do something like this:
$ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic
QEMU 2.9.93 monitor - type 'help' for more information
(qemu) device_add allwinner-a10
Unsupported NIC model: smc91c111
Exiting just due to a "device_add" should not happen. Looking closer
at the the realize and instance_init function of this device also
reveals that it is using serial_hds and nd_table directly there, so
this device is clearly not creatable by the user and should be marked
accordingly.
Signed-off-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com>
Message-id: 1503416789-32080-1-git-send-email-th...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 0e1a46bbd2d6c39614b87f4e88ea305acce8a35f
https://github.com/qemu/qemu/commit/0e1a46bbd2d6c39614b87f4e88ea305acce8a35f
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
target/arm: Implement ARMv8M's PMSAv8 registers
As part of ARMv8M, we need to add support for the PMSAv8 MPU
architecture.
PMSAv8 differs from PMSAv7 both in register/data layout (for instance
using base and limit registers rather than base and size) and also in
behaviour (for example it does not have subregions); rather than
trying to wedge it into the existing PMSAv7 code and data structures,
we define separate ones.
This commit adds the data structures which hold the state for a
PMSAv8 MPU and the register interface to it. The implementation of
the MPU behaviour will be added in a subsequent commit.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-2-git-send-email-peter.mayd...@linaro.org
Commit: 504e3cc36b68b34c176f3f4116b1d5677471ec20
https://github.com/qemu/qemu/commit/504e3cc36b68b34c176f3f4116b1d5677471ec20
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement new PMSAv8 behaviour
Implement the behavioural side of the new PMSAv8 specification.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-3-git-send-email-peter.mayd...@linaro.org
Commit: 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f
https://github.com/qemu/qemu/commit/1e577cc7cffd3de14dbd321de5c3ef191c6ab07f
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Add state field, feature bit and migration for v8M secure state
As the first step in implementing ARM v8M's security extension:
* add a new feature bit ARM_FEATURE_M_SECURITY
* add the CPU state field that indicates whether the CPU is
currently in the secure state
* add a migration subsection for this new state
(we will add the Secure copies of banked register state
to this subsection in later patches)
* add a #define for the one new-in-v8M exception type
* make the CPU debug log print S/NS status
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-4-git-send-email-peter.mayd...@linaro.org
Commit: 1d2091bc75ab7f9e2c43082f361a528a63c79527
https://github.com/qemu/qemu/commit/1d2091bc75ab7f9e2c43082f361a528a63c79527
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Register second AddressSpace for secure v8M CPUs
If a v8M CPU supports the security extension then we need to
give it two AddressSpaces, the same way we do already for
an A profile core with EL3.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-5-git-send-email-peter.mayd...@linaro.org
Commit: 66787c7868d05d29974e09201611b718c976f955
https://github.com/qemu/qemu/commit/66787c7868d05d29974e09201611b718c976f955
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add MMU indexes for secure v8M
Now that MPU lookups can return different results for v8M
when the CPU is in secure vs non-secure state, we need to
have separate MMU indexes; add the secure counterparts
to the existing three M profile MMU indexes.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-6-git-send-email-peter.mayd...@linaro.org
Commit: acf949411ffb675edbfb707e235800b02e6a36f8
https://github.com/qemu/qemu/commit/acf949411ffb675edbfb707e235800b02e6a36f8
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make BASEPRI register banked for v8M
Make the BASEPRI register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to
be restricted).
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-7-git-send-email-peter.mayd...@linaro.org
Commit: 6d8048341995b31a77dc2e0dcaaf4e3df0e3121a
https://github.com/qemu/qemu/commit/6d8048341995b31a77dc2e0dcaaf4e3df0e3121a
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make PRIMASK register banked for v8M
Make the PRIMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to
be restricted).
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-8-git-send-email-peter.mayd...@linaro.org
Commit: 42a6686b2f6199d086a58edd7731faeb2dbe7c14
https://github.com/qemu/qemu/commit/42a6686b2f6199d086a58edd7731faeb2dbe7c14
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make FAULTMASK register banked for v8M
Make the FAULTMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to
be restricted).
This patch includes the code to determine for v8M which copy
of FAULTMASK should be updated on exception exit; further
changes will be required to the exception exit code in general
to support v8M, so this is just a small piece of that.
The v8M ARM ARM introduces a notation where individual paragraphs
are labelled with R (for rule) or I (for information) followed
by a random group of subscript letters. In comments where we want
to refer to a particular part of the manual we use this convention,
which should be more stable across document revisions than using
section or page numbers.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-9-git-send-email-peter.mayd...@linaro.org
Commit: 8bfc26ea302ec03585d7258a7cf8938f76512730
https://github.com/qemu/qemu/commit/8bfc26ea302ec03585d7258a7cf8938f76512730
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Make CONTROL register banked for v8M
Make the CONTROL register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-10-git-send-email-peter.mayd...@linaro.org
Commit: f104919d15a3f0be57a70b5499bc9fa5e06224fd
https://github.com/qemu/qemu/commit/f104919d15a3f0be57a70b5499bc9fa5e06224fd
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M include/hw/intc/armv7m_nvic.h
Log Message:
-----------
nvic: Add NS alias SCS region
For v8M the range 0xe002e000..0xe002efff is an alias region which
for secure accesses behaves like a NonSecure access to the main
SCS region. (For nonsecure accesses including when the security
extension is not implemented, it is RAZ/WI.)
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 1503414539-28762-11-git-send-email-peter.mayd...@linaro.org
Commit: 45db7ba681ede57113a67499840e69ee586bcdf2
https://github.com/qemu/qemu/commit/45db7ba681ede57113a67499840e69ee586bcdf2
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make VTOR register banked for v8M
Make the VTOR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-12-git-send-email-peter.mayd...@linaro.org
Commit: 4125e6feb71c810ca38f0d8e66e748b472a9cc54
https://github.com/qemu/qemu/commit/4125e6feb71c810ca38f0d8e66e748b472a9cc54
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-13-git-send-email-peter.mayd...@linaro.org
Commit: 62c58ee0b24eafb44c06402fe059fbd7972eb409
https://github.com/qemu/qemu/commit/62c58ee0b24eafb44c06402fe059fbd7972eb409
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.
We can freely add more items to vmstate_m_security without
breaking migration compatibility, because no CPU currently
has the ARM_FEATURE_M_SECURITY bit enabled and so this
subsection is not yet used by anything.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-14-git-send-email-peter.mayd...@linaro.org
Commit: 1bc04a8880374407c4b12d82ceb8752e12ff5336
https://github.com/qemu/qemu/commit/1bc04a8880374407c4b12d82ceb8752e12ff5336
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make MPU_RNR register banked for v8M
Make the MPU_RNR register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-15-git-send-email-peter.mayd...@linaro.org
Commit: ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9
https://github.com/qemu/qemu/commit/ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make MPU_CTRL register banked for v8M
Make the MPU_CTRL register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-16-git-send-email-peter.mayd...@linaro.org
Commit: 9d40cd8a68cfc7606f4548cc9e812bab15c6dc28
https://github.com/qemu/qemu/commit/9d40cd8a68cfc7606f4548cc9e812bab15c6dc28
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make CCR register banked for v8M
Make the CCR register banked if v8M security extensions are enabled.
This is slightly more complicated than the other "add banking"
patches because there is one bit in the register which is not
banked. We keep the live data in the NS copy of the register,
and adjust it on register reads and writes. (Since we don't
currently implement the behaviour that the bit controls, there
is nowhere else that needs to care.)
This patch includes the enforcement of the bits which are newly
RES1 in ARMv8M.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 1503414539-28762-17-git-send-email-peter.mayd...@linaro.org
Commit: c51a5cfc9fae82099028eb12cb1d064ee07f348e
https://github.com/qemu/qemu/commit/c51a5cfc9fae82099028eb12cb1d064ee07f348e
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make MMFAR banked for v8M
Make the MMFAR register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-18-git-send-email-peter.mayd...@linaro.org
Commit: 334e8dad7a109d15cb20b090131374ae98682a50
https://github.com/qemu/qemu/commit/334e8dad7a109d15cb20b090131374ae98682a50
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Make CFSR register banked for v8M
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR
bits [15:8] are shared between S and NS, and we store them
in the NS copy of the register.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-19-git-send-email-peter.mayd...@linaro.org
Commit: 61fcd69b0db268e7612b07fadc436b93def91768
https://github.com/qemu/qemu/commit/61fcd69b0db268e7612b07fadc436b93def91768
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move regime_is_secure() to target/arm/internals.h
Move the regime_is_secure() utility function to internals.h;
we are going to want to call it from translate.c.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-20-git-send-email-peter.mayd...@linaro.org
Commit: fb602cb726b3ebdd01ef3b1732d74baf9fee7ec9
https://github.com/qemu/qemu/commit/fb602cb726b3ebdd01ef3b1732d74baf9fee7ec9
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/machine.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement BXNS, and banked stack pointers
Implement the BXNS v8M instruction, which is like BX but will do a
jump-and-switch-to-NonSecure if the branch target address has bit 0
clear.
This is the first piece of code which implements "switch to the
other security state", so the commit also includes the code to
switch the stack pointers around, which is the only complicated
part of switching security state.
BLXNS is more complicated than just "BXNS but set the link register",
so we leave it for a separate commit.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1503414539-28762-21-git-send-email-peter.mayd...@linaro.org
Commit: ed860129acd3fcd0b1e47884e810212aaca4d21b
https://github.com/qemu/qemu/commit/ed860129acd3fcd0b1e47884e810212aaca4d21b
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M include/hw/boards.h
M include/qom/cpu.h
M qom/cpu.c
Log Message:
-----------
boards.h: Define new flag ignore_memory_transaction_failures
Define a new MachineClass field ignore_memory_transaction_failures.
If this is flag is true then the CPU will ignore memory transaction
failures which should cause the CPU to take an exception due to an
access to an unassigned physical address; the transaction will
instead return zero (for a read) or be ignored (for a write). This
should be set only by legacy board models which rely on the old
RAZ/WI behaviour for handling devices that QEMU does not yet model.
New board models should instead use "unimplemented-device" for all
memory ranges where the guest will attempt to probe for a device that
QEMU doesn't implement and a stub device is required.
We need this for ARM boards, where we're about to implement support for
generating external aborts on memory transaction failures. Too many
of our legacy board models rely on the RAZ/WI behaviour and we
would break currently working guests when their "probe for device"
code provoked an external abort rather than a RAZ.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Message-id: 1504626814-23124-2-git-send-email-peter.mayd...@linaro.org
Commit: 4672cbd7bed88dc67f089e84a0fd5d7739020c92
https://github.com/qemu/qemu/commit/4672cbd7bed88dc67f089e84a0fd5d7739020c92
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/collie.c
M hw/arm/cubieboard.c
M hw/arm/digic_boards.c
M hw/arm/exynos4_boards.c
M hw/arm/gumstix.c
M hw/arm/highbank.c
M hw/arm/imx25_pdk.c
M hw/arm/integratorcp.c
M hw/arm/kzm.c
M hw/arm/mainstone.c
M hw/arm/musicpal.c
M hw/arm/netduino2.c
M hw/arm/nseries.c
M hw/arm/omap_sx1.c
M hw/arm/palm.c
M hw/arm/raspi.c
M hw/arm/realview.c
M hw/arm/sabrelite.c
M hw/arm/spitz.c
M hw/arm/stellaris.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/vexpress.c
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-ep108.c
M hw/arm/z2.c
Log Message:
-----------
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
Set the MachineClass flag ignore_memory_transaction_failures
for almost all ARM boards. This means they retain the legacy
behaviour that accesses to unimplemented addresses will RAZ/WI
rather than aborting, when a subsequent commit adds support
for external aborts.
The exceptions are:
* virt -- we know that guests won't try to prod devices
that we don't describe in the device tree or ACPI tables
* mps2 -- this board was written to use unimplemented-device
for all the ranges with devices we don't yet handle
New boards should not set the flag, but instead be written
like the mps2.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Message-id: 1504626814-23124-3-git-send-email-peter.mayd...@linaro.org
For the Xilinx boards:
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Commit: c79c0a314c43b78f6326d5f137bdbafdbf8e9766
https://github.com/qemu/qemu/commit/c79c0a314c43b78f6326d5f137bdbafdbf8e9766
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Implement new do_transaction_failed hook
Implement the new do_transaction_failed hook for ARM, which should
cause the CPU to take a prefetch abort or data abort.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Message-id: 1504626814-23124-4-git-send-email-peter.mayd...@linaro.org
Commit: c99a55d38dd5b5131f3fcbbaf41828a09ee62544
https://github.com/qemu/qemu/commit/c99a55d38dd5b5131f3fcbbaf41828a09ee62544
Author: Portia Stephens <portia.steph...@xilinx.com>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Add Jazelle feature
This adds a feature bit indicating support of the (trivial) Jazelle
implementation if ARM_FEATURE_V6 is set or if the processor is arm926
or arm1026. This fixes the issue that any BXJ instruction will
result in an illegal_op. BXJ instructions will now check if the
architecture supports ARM_FEATURE_JAZELLE.
Signed-off-by: Portia Stephens <portia.steph...@xilinx.com>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Message-id: 20170905211232.11092-1-portia.steph...@xilinx.com
[PMM: edited commit message and comment text a bit]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: ef475b5dd12684591e6264e517eaa5b3e90f7ffa
https://github.com/qemu/qemu/commit/ef475b5dd12684591e6264e517eaa5b3e90f7ffa
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2017-09-07 (Thu, 07 Sep 2017)
Changed paths:
M hw/arm/allwinner-a10.c
M hw/arm/armv7m.c
M hw/arm/aspeed.c
M hw/arm/collie.c
M hw/arm/cubieboard.c
M hw/arm/digic_boards.c
M hw/arm/exynos4_boards.c
M hw/arm/gumstix.c
M hw/arm/highbank.c
M hw/arm/imx25_pdk.c
M hw/arm/integratorcp.c
M hw/arm/kzm.c
M hw/arm/mainstone.c
M hw/arm/musicpal.c
M hw/arm/netduino2.c
M hw/arm/nseries.c
M hw/arm/omap_sx1.c
M hw/arm/palm.c
M hw/arm/raspi.c
M hw/arm/realview.c
M hw/arm/sabrelite.c
M hw/arm/spitz.c
M hw/arm/stellaris.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/vexpress.c
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-ep108.c
M hw/arm/xlnx-zynqmp.c
M hw/arm/z2.c
M hw/dma/xilinx_axidma.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/armv7m_nvic.c
M hw/net/xilinx_axienet.c
M include/hw/boards.h
M include/hw/intc/armv7m_nvic.h
M include/qom/cpu.h
M qom/cpu.c
M scripts/device-crash-test
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/machine.c
M target/arm/op_helper.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'
into staging
target-arm:
* cleanups converting to DEFINE_PROP_LINK
* allwinner-a10: mark as not user-creatable
* initial patches working towards ARMv8M support
* implement generating aborts on memory transaction failures
* make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later
# gpg: Signature made Thu 07 Sep 2017 14:26:07 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg: aka "Peter Maydell <pmayd...@gmail.com>"
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits)
target/arm: Add Jazelle feature
target/arm: Implement new do_transaction_failed hook
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
boards.h: Define new flag ignore_memory_transaction_failures
target/arm: Implement BXNS, and banked stack pointers
target/arm: Move regime_is_secure() to target/arm/internals.h
target/arm: Make CFSR register banked for v8M
target/arm: Make MMFAR banked for v8M
target/arm: Make CCR register banked for v8M
target/arm: Make MPU_CTRL register banked for v8M
target/arm: Make MPU_RNR register banked for v8M
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
target/arm: Make VTOR register banked for v8M
nvic: Add NS alias SCS region
target/arm: Make CONTROL register banked for v8M
target/arm: Make FAULTMASK register banked for v8M
target/arm: Make PRIMASK register banked for v8M
target/arm: Make BASEPRI register banked for v8M
target/arm: Add MMU indexes for secure v8M
...
# Conflicts:
# target/arm/translate.c
Compare: https://github.com/qemu/qemu/compare/7794b34e63fd...ef475b5dd126
