Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 1cf134f1e8315456991186af53e5a6ddca94aaa2
https://github.com/qemu/qemu/commit/1cf134f1e8315456991186af53e5a6ddca94aaa2
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Replace DISAS_TB_JUMP with DISAS_NORETURN
The only semantic of DISAS_TB_JUMP is that we've done goto_tb,
which is the same as DISAS_NORETURN -- we've exited the tb.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 12f9387f5c873f462ad0f21e38d96b9e276a23b7
https://github.com/qemu/qemu/commit/12f9387f5c873f462ad0f21e38d96b9e276a23b7
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Use global cpu_env
We do not need to copy this into DisasContext.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 438aabed0a44438c4a5f40d7abb3be2ffb0a8d48
https://github.com/qemu/qemu/commit/438aabed0a44438c4a5f40d7abb3be2ffb0a8d48
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Use global cpu_R
We do not need to copy this into DisasContext.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e9150ea5231683c5a591a8e3ae120abd2c970707
https://github.com/qemu/qemu/commit/e9150ea5231683c5a591a8e3ae120abd2c970707
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Add DisasContextBase to DisasContext
Migrate the is_jmp, tb and singlestep_enabled fields from
DisasContext into the base. Use pc_first instead of tb->pc.
Increment pc_next prior to decode, leaving the address of
the current insn in dc->pc.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: d67cbd932187fecf70d38bd113fa985209b72671
https://github.com/qemu/qemu/commit/d67cbd932187fecf70d38bd113fa985209b72671
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Convert to TranslatorOps
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 50e1a0cd3cf7cc2b56fee6523882014fda95dc95
https://github.com/qemu/qemu/commit/50e1a0cd3cf7cc2b56fee6523882014fda95dc95
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Remove assignment to env in handle_instruction
Direct assignments to env during translation do not work.
As it happens, the only way we can get here is if env->pc
is already set to dc->pc. We will trap on the first insn
we execute anywhere on the page.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a5f919d19c60d2085fdef4bf5c750b439c589c0a
https://github.com/qemu/qemu/commit/a5f919d19c60d2085fdef4bf5c750b439c589c0a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Clean up goto in handle_instruction
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1ff375d743724d4a31b6cebcf97961e24645eb71
https://github.com/qemu/qemu/commit/1ff375d743724d4a31b6cebcf97961e24645eb71
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Inline handle_instruction
Move handle_instruction into nios2_tr_translate_insn
as the only caller.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 77b42a2d53e27144451ca9b5de628bfe86edde1b
https://github.com/qemu/qemu/commit/77b42a2d53e27144451ca9b5de628bfe86edde1b
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Use pc_next for pc + 4
We have pre-computed the next instruction address into
dc->base.pc_next, so we might as well use it.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Suggested-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 93d4d5e485e2ab86dd7f1403f0782c8dbedeebcd
https://github.com/qemu/qemu/commit/93d4d5e485e2ab86dd7f1403f0782c8dbedeebcd
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/avr/translate.c
Log Message:
-----------
target/avr: Add DisasContextBase to DisasContext
Migrate the bstate, tb and singlestep_enabled fields
from DisasContext into the base.
Tested-by: Michael Rolnik <mrol...@gmail.com>
Reviewed-by: Michael Rolnik <mrol...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: bcef6d7601da9f5aae632f265ec4ec6231df4677
https://github.com/qemu/qemu/commit/bcef6d7601da9f5aae632f265ec4ec6231df4677
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/avr/translate.c
Log Message:
-----------
target/avr: Change ctx to DisasContext* in gen_intermediate_code
Prepare for receiving it as a pointer input.
Tested-by: Michael Rolnik <mrol...@gmail.com>
Reviewed-by: Michael Rolnik <mrol...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3fbd28d88f80f17691ecd17dc4ad4c2e354a03ba
https://github.com/qemu/qemu/commit/3fbd28d88f80f17691ecd17dc4ad4c2e354a03ba
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/avr/translate.c
Log Message:
-----------
target/avr: Convert to TranslatorOps
Tested-by: Michael Rolnik <mrol...@gmail.com>
Reviewed-by: Michael Rolnik <mrol...@gmail.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 67f69c4c15216f083bc81419e958c795b58bbbef
https://github.com/qemu/qemu/commit/67f69c4c15216f083bc81419e958c795b58bbbef
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
M target/cris/translate_v10.c.inc
Log Message:
-----------
target/cris: Add DisasContextBase to DisasContext
Migrate the is_jmp, tb and singlestep_enabled fields
from DisasContext into the base.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 6abfa161aab590dc84498fd2c3feceabbae60ec6
https://github.com/qemu/qemu/commit/6abfa161aab590dc84498fd2c3feceabbae60ec6
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Remove DISAS_SWI
This value is unused.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a67f11b1d9fe29a2e2f66b74d032fbe832b9131e
https://github.com/qemu/qemu/commit/a67f11b1d9fe29a2e2f66b74d032fbe832b9131e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN
The only semantic of DISAS_TB_JUMP is that we've done goto_tb,
which is the same as DISAS_NORETURN -- we've exited the tb.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1dd09c47f69be6e9dbdf18248730b2e20d72d1ef
https://github.com/qemu/qemu/commit/1dd09c47f69be6e9dbdf18248730b2e20d72d1ef
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
M target/cris/translate_v10.c.inc
Log Message:
-----------
target/cris: Mark exceptions as DISAS_NORETURN
After we've raised the exception, we have left the TB.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 06188c8981ca5d5386e22c82d5bd40e5f27c8492
https://github.com/qemu/qemu/commit/06188c8981ca5d5386e22c82d5bd40e5f27c8492
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Fix use_goto_tb
Do not skip the page check for user-only -- mmap/mprotect can
still change page mappings. Only check dc->base.pc_first, not
dc->ppc -- the start page is the only one that's relevant.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 330ca14bcec1927f058e5e51ee33d9436e93a943
https://github.com/qemu/qemu/commit/330ca14bcec1927f058e5e51ee33d9436e93a943
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Convert to TranslatorOps
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 71fc4615c644fcd9c30141652af0679a644aa636
https://github.com/qemu/qemu/commit/71fc4615c644fcd9c30141652af0679a644aa636
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/helper.h
Log Message:
-----------
target/cris: Mark helper_raise_exception noreturn
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5899ce683edab9c8f6e1d46867245e0c3564eadc
https://github.com/qemu/qemu/commit/5899ce683edab9c8f6e1d46867245e0c3564eadc
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
M target/cris/translate_v10.c.inc
Log Message:
-----------
target/cris: Mark static arrays const
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: afd5a3310c073bf0dfdbb5caaa9f70803d0798be
https://github.com/qemu/qemu/commit/afd5a3310c073bf0dfdbb5caaa9f70803d0798be
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Fold unhandled X_FLAG changes into cpustate_changed
We really do this already, by including them into the same test.
This just hoists the expression up a bit.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9e9f5ba071a425e0bc2315a66115c0e6924455b3
https://github.com/qemu/qemu/commit/9e9f5ba071a425e0bc2315a66115c0e6924455b3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Set cpustate_changed for rfe/rfn
These insns set DISAS_UPDATE without cpustate_changed,
which isn't quite right.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c96747521c5142ea3c2cba687ff09be405d4054a
https://github.com/qemu/qemu/commit/c96747521c5142ea3c2cba687ff09be405d4054a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Add DISAS_UPDATE_NEXT
Move this pc update into tb_stop.
We will be able to re-use this code shortly.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3173715195a2cb7c92e89ca478a6ee86fe9551f0
https://github.com/qemu/qemu/commit/3173715195a2cb7c92e89ca478a6ee86fe9551f0
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Add DISAS_DBRANCH
Move delayed branch handling to tb_stop, where we can re-use other
end-of-tb code, e.g. the evaluation of flags. Honor single stepping.
Validate that we aren't losing state by overwriting is_jmp.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e0a4620c1f8011cb2b638f9013e087b53ca325ad
https://github.com/qemu/qemu/commit/e0a4620c1f8011cb2b638f9013e087b53ca325ad
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Use tcg_gen_lookup_and_goto_ptr
We can use this in gen_goto_tb and for DISAS_JUMP
to indirectly chain to the next TB.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3a1a80cc052377134a7d8c1c008085de3413cf61
https://github.com/qemu/qemu/commit/3a1a80cc052377134a7d8c1c008085de3413cf61
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Improve JMP_INDIRECT
Use movcond instead of brcond to set env_pc.
Discard the btarget and btaken variables to improve
register allocation and avoid unnecessary writeback.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0ce97a315fe16ab104cafe459b2c946a63000e08
https://github.com/qemu/qemu/commit/0ce97a315fe16ab104cafe459b2c946a63000e08
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
M target/cris/translate_v10.c.inc
Log Message:
-----------
target/cris: Remove dc->flagx_known
Ever since 2a44f7f17364, flagx_known is always true.
Fold away all of the tests against the flag.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5f5a05cdd9aa4dc3c3c4b062de2a8494f23337ed
https://github.com/qemu/qemu/commit/5f5a05cdd9aa4dc3c3c4b062de2a8494f23337ed
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/cris/translate.c
Log Message:
-----------
target/cris: Do not exit tb for X_FLAG changes
We always know the exact value of X, that's all that matters.
This avoids splitting the TB e.g. between "ax" and "addq".
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3d066e5d8008f8537e46f5ead37ecbdb4922a221
https://github.com/qemu/qemu/commit/3d066e5d8008f8537e46f5ead37ecbdb4922a221
Author: LIU Zhiwei <zhiwei_...@c-sky.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_vec_add{sub}16_i32
Implement tcg_gen_vec_add{sub}16_tl by adding corresponding i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Message-Id: <20210624105023.3852-2-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 448e7aa28c147002373919d65f401ee4a5432a72
https://github.com/qemu/qemu/commit/448e7aa28c147002373919d65f401ee4a5432a72
Author: LIU Zhiwei <zhiwei_...@c-sky.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_vec_add{sub}8_i32
Implement tcg_gen_vec_add{sub}8_tl by adding corresponging i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Message-Id: <20210624105023.3852-3-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 04f2a8bbc019ad858cd7ec4f89b34e15f96eef4e
https://github.com/qemu/qemu/commit/04f2a8bbc019ad858cd7ec4f89b34e15f96eef4e
Author: LIU Zhiwei <zhiwei_...@c-sky.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32
Implement tcg_gen_vec_shl{shr}{sar}16i_tl by adding corresponging i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Message-Id: <20210624105023.3852-4-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 950ee59026d2ed524b0e2e0b84e5e8feb3b080e5
https://github.com/qemu/qemu/commit/950ee59026d2ed524b0e2e0b84e5e8feb3b080e5
Author: LIU Zhiwei <zhiwei_...@c-sky.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op-gvec.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32
Implement tcg_gen_vec_shl{shr}{sar}8i_tl by adding corresponging i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Message-Id: <20210624105023.3852-5-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7f05d32f581ce2c6f8c9f4f39ad6b35143361f14
https://github.com/qemu/qemu/commit/7f05d32f581ce2c6f8c9f4f39ad6b35143361f14
Author: LIU Zhiwei <zhiwei_...@c-sky.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op-gvec.h
Log Message:
-----------
tcg: Implement tcg_gen_vec_add{sub}32_tl
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Message-Id: <20210624105023.3852-6-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4f862f79ca497f68d147520e847f86d69eec950b
https://github.com/qemu/qemu/commit/4f862f79ca497f68d147520e847f86d69eec950b
Author: Warner Losh <i...@bsdimp.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M accel/tcg/user-exec.c
Log Message:
-----------
tcg: Use correct trap number for page faults on *BSD systems
The trap number for a page fault on BSD systems is T_PAGEFLT
not 0xe -- 0xe is used by Linux and represents the intel hardware
trap vector. The BSD kernels, however, translate this to T_PAGEFLT
in their Xpage, Xtrap0e, Xtrap14, etc fault handlers. This is true
for i386 and x86_64, though the name of the trap hanlder can very
on the flavor of BSD. As far as I can tell, Linux doesn't provide
a define for this value. Invent a new one (PAGE_FAULT_TRAP) and
use it instead to avoid uglier ifdefs.
Signed-off-by: Mark Johnston <ma...@freebsd.org>
Signed-off-by: Juergen Lock <n...@freebsd.org>
[ Rework to avoid ifdefs and expand it to i386 ]
Signed-off-by: Warner Losh <i...@bsdimp.com>
Message-Id: <20210625045707.84534-3-...@bsdimp.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 587195bd5905deefe90242bbd210b9bba76ca093
https://github.com/qemu/qemu/commit/587195bd5905deefe90242bbd210b9bba76ca093
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M tcg/README
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Add flags argument to bswap opcodes
This will eventually simplify front-end usage, and will allow
backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of
optimization.
The argument is added during expansion, not currently exposed to the
front end translators. The backends currently only support a flags
value of either TCG_BSWAP_IZ, or (TCG_BSWAP_IZ | TCG_BSWAP_OZ),
since they all require zero top bytes and leave them that way.
At the existing call sites we pass in (TCG_BSWAP_IZ | TCG_BSWAP_OZ),
except for the flags-ignored cases of a 32-bit swap of a 32-bit
value and or a 64-bit swap of a 64-bit value, where we pass 0.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7335a3d69fdbd4a22a3bafc8b62c44c99e63880b
https://github.com/qemu/qemu/commit/7335a3d69fdbd4a22a3bafc8b62c44c99e63880b
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Support bswap flags
Retain the current rorw bswap16 expansion for the zero-in/zero-out case.
Otherwise, perform a wider bswap plus a right-shift or extend.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: dfa24dfa096ca8186b35aa001419d978ee1e5638
https://github.com/qemu/qemu/commit/dfa24dfa096ca8186b35aa001419d978ee1e5638
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Merge tcg_out_rev{16,32,64}
Pass in the input and output size. We currently use 3 of the 5
possible combinations; the others may be used by new tcg opcodes.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 8fcfc6bff61f1faf0a530b4fae292931a39cc32b
https://github.com/qemu/qemu/commit/8fcfc6bff61f1faf0a530b4fae292931a39cc32b
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Support bswap flags
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 2ec89a78a518c4275c6a56ba51b6e1b8ab9e8199
https://github.com/qemu/qemu/commit/2ec89a78a518c4275c6a56ba51b6e1b8ab9e8199
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Support bswap flags
Combine the three bswap16 routines, and differentiate via the flags.
Use the correct flags combination from the load/store routines, and
pass along the constant parameter from tcg_out_op.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: f4bf14f4018b6fb57bdd9566fce874da691a6369
https://github.com/qemu/qemu/commit/f4bf14f4018b6fb57bdd9566fce874da691a6369
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Split out tcg_out_ext{8,16,32}s
We will shortly require these in other context;
make the expansion as clear as possible.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 05dd01fa5ade816899dcf104e71ecf8a90577301
https://github.com/qemu/qemu/commit/05dd01fa5ade816899dcf104e71ecf8a90577301
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Split out tcg_out_sari{32,64}
We will shortly require sari in other context;
split out both for cleanliness sake.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 783d3ecdda97f0f332afa9de1cfa6fac100db31c
https://github.com/qemu/qemu/commit/783d3ecdda97f0f332afa9de1cfa6fac100db31c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Split out tcg_out_bswap16
With the use of a suitable temporary, we can use the same
algorithm when src overlaps dst. The result is the same
number of instructions either way.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 8a611d8640c0a2d09fd3ca7af893230fe124bdc5
https://github.com/qemu/qemu/commit/8a611d8640c0a2d09fd3ca7af893230fe124bdc5
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Split out tcg_out_bswap32
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 674ba58803e1e609b921601ecbfdbc19ab12c102
https://github.com/qemu/qemu/commit/674ba58803e1e609b921601ecbfdbc19ab12c102
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Split out tcg_out_bswap64
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 26ce70051b88664ce8c50a1c869766be88c7f110
https://github.com/qemu/qemu/commit/26ce70051b88664ce8c50a1c869766be88c7f110
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Support bswap flags
For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
output does not need extension within the host 64-bit register.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 780b573fcec68bd35878e886bea418c2b74f1fe5
https://github.com/qemu/qemu/commit/780b573fcec68bd35878e886bea418c2b74f1fe5
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use power10 byte-reverse instructions
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1619ee9e93ed8f7bbbae61b946c56bd34713d4ac
https://github.com/qemu/qemu/commit/1619ee9e93ed8f7bbbae61b946c56bd34713d4ac
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/s390/tcg-target.c.inc
Log Message:
-----------
tcg/s390: Support bswap flags
For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
easily provide the extension to 64-bits. Drop the special case,
previously used, where the input is already zero-extended -- the
minor code size savings is not worth the complication.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 27362b7b2c5a4565c41ac2fb1ff3d4e0b1e6534e
https://github.com/qemu/qemu/commit/27362b7b2c5a4565c41ac2fb1ff3d4e0b1e6534e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Support bswap flags in tcg_out_bswap16
Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
in the internal uses for loads and stores.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1fce6534403c7b8741f8eb6a3528142c86c1bd93
https://github.com/qemu/qemu/commit/1fce6534403c7b8741f8eb6a3528142c86c1bd93
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Support bswap flags in tcg_out_bswap32
Merge tcg_out_bswap32 and tcg_out_bswap32s.
Use the flags in the internal uses for loads and stores.
For mips32r2 bswap32 with zero-extension, standardize on
WSBH+ROTR+DEXT. This is the same number of insns as the
previous DSBH+DSHD+DSRL but fits in better with the flags check.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0d57d36af5de88f86e4ec1e1abc716209f791f8f
https://github.com/qemu/qemu/commit/0d57d36af5de88f86e4ec1e1abc716209f791f8f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Support bswap flags
The existing interpreter zero-extends, ignoring high bits.
Simply add a separate sign-extension opcode if required.
Ensure that the interpreter supports ext16s when bswap16 is enabled.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0b76ff8f1b63733f3cae78e4a0aba332e994f8d8
https://github.com/qemu/qemu/commit/0b76ff8f1b63733f3cae78e4a0aba332e994f8d8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg: Handle new bswap flags during optimize
Notice when the input is known to be zero-extended and force
the TCG_BSWAP_IZ flag on. Honor the TCG_BSWAP_OS bit during
constant folding. Propagate the input to the output mask.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 2b836c2ac1d040bbe2e47fd000924083fbcef414
https://github.com/qemu/qemu/commit/2b836c2ac1d040bbe2e47fd000924083fbcef414
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M include/tcg/tcg-op.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/i386/tcg/translate.c
M target/mips/tcg/mxu_translate.c
M target/s390x/translate.c
M target/sh4/translate.c
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
Implement the new semantics in the fallback expansion.
Change all callers to supply the flags that keep the
semantics unchanged locally.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 359feba534b3473471d35934ffd66781aaff468d
https://github.com/qemu/qemu/commit/359feba534b3473471d35934ffd66781aaff468d
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Make use of bswap flags in tcg_gen_qemu_ld_*
We can perform any required sign-extension via TCG_BSWAP_OS.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b53357acb4d2c96adaf4dbf1f21999b0e1cf5bda
https://github.com/qemu/qemu/commit/b53357acb4d2c96adaf4dbf1f21999b0e1cf5bda
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Make use of bswap flags in tcg_gen_qemu_st_*
By removing TCG_BSWAP_IZ we indicate that the input is
not zero-extended, and thus can remove an explicit extend.
By removing TCG_BSWAP_OZ, we allow the implementation to
leave high bits set, which will be ignored by the store.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 2b0a39e51e64ae501192b18233bddcc81c098312
https://github.com/qemu/qemu/commit/2b0a39e51e64ae501192b18233bddcc81c098312
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Improve REV32
For the sf version, we are performing two 32-bit bswaps
in either half of the register. This is equivalent to
performing one 64-bit bswap followed by a rotate.
For the non-sf version, we can remove TCG_BSWAP_IZ
and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 50a7470e3e9de7fda510acd02880f85ad6d5afd5
https://github.com/qemu/qemu/commit/50a7470e3e9de7fda510acd02880f85ad6d5afd5
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Improve vector REV
We can eliminate the requirement for a zero-extended output,
because the following store will ignore any garbage high bits.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: ebdd503d4572cc446a9a61410755cc3b87e2d76f
https://github.com/qemu/qemu/commit/ebdd503d4572cc446a9a61410755cc3b87e2d76f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Improve REVSH
The new bswap flags can implement the semantics exactly.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 94fdf98721943e79a02a06f4aa3c92f2c8f2e409
https://github.com/qemu/qemu/commit/94fdf98721943e79a02a06f4aa3c92f2c8f2e409
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Improve bswap translation
Use a break instead of an ifdefed else.
There's no need to move the values through s->T0.
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b983a0e17240fcbc8e1a32ef44221a1954332c81
https://github.com/qemu/qemu/commit/b983a0e17240fcbc8e1a32ef44221a1954332c81
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Improve swap.b translation
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 92ecfab50ee2b30e60c774f96f05fc38714874f1
https://github.com/qemu/qemu/commit/92ecfab50ee2b30e60c774f96f05fc38714874f1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips: Fix gen_mxu_s32ldd_s32lddr
There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.
The best fix is to fold the bswap into the memory operation,
producing the desired result directly.
Acked-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 843b82424f9554a48f8ade0e1e3ffb20709f0801
https://github.com/qemu/qemu/commit/843b82424f9554a48f8ade0e1e3ffb20709f0801
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
Now that the middle-end can replicate the same tricks as tcg/arm
used for optimizing bswap for signed loads and for stores, do not
pretend to have these memory ops in the backend.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 51c559c761de3ee94b06e931454d86995d86d013
https://github.com/qemu/qemu/commit/51c559c761de3ee94b06e931454d86995d86d013
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
Log Message:
-----------
tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP
The memory bswap support in the aarch64 backend merely dates from
a time when it was required. There is nothing special about the
backend support that could not have been provided by the middle-end
even prior to the introduction of the bswap flags.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c86bd2dc4c1d37653c27293b2dacee6bb46bb995
https://github.com/qemu/qemu/commit/c86bd2dc4c1d37653c27293b2dacee6bb46bb995
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Remove MO_BSWAP handling
TCG_TARGET_HAS_MEMORY_BSWAP is already unset for this backend,
which means that MO_BSWAP be handled by the middle-end and
will never be seen by the backend. Thus the indexes used with
qemu_{ld,st}_helpers will always be zero.
Tidy the comments and asserts in tcg_out_qemu_{ld,st}_direct.
It is not that we do not handle bswap "yet", but never will.
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 67e25eed977cb60e723b918207f0a3469baceef4
https://github.com/qemu/qemu/commit/67e25eed977cb60e723b918207f0a3469baceef4
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2021-07-01 (Thu, 01 Jul 2021)
Changed paths:
M accel/tcg/user-exec.c
M include/tcg/tcg-op-gvec.h
M include/tcg/tcg-op.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/avr/translate.c
M target/cris/helper.h
M target/cris/translate.c
M target/cris/translate_v10.c.inc
M target/i386/tcg/translate.c
M target/mips/tcg/mxu_translate.c
M target/nios2/translate.c
M target/s390x/translate.c
M target/sh4/translate.c
M tcg/README
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/tcg-op-gvec.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into
staging
TranslatorOps conversion for target/avr
TranslatorOps conversion for target/cris
TranslatorOps conversion for target/nios2
Simple vector operations on TCGv_i32
Host signal fixes for *BSD
Improvements to tcg bswap operations
# gpg: Signature made Tue 29 Jun 2021 19:51:03 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.hender...@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210629: (63 commits)
tcg/riscv: Remove MO_BSWAP handling
tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP
tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
target/mips: Fix gen_mxu_s32ldd_s32lddr
target/sh4: Improve swap.b translation
target/i386: Improve bswap translation
target/arm: Improve REVSH
target/arm: Improve vector REV
target/arm: Improve REV32
tcg: Make use of bswap flags in tcg_gen_qemu_st_*
tcg: Make use of bswap flags in tcg_gen_qemu_ld_*
tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
tcg: Handle new bswap flags during optimize
tcg/tci: Support bswap flags
tcg/mips: Support bswap flags in tcg_out_bswap32
tcg/mips: Support bswap flags in tcg_out_bswap16
tcg/s390: Support bswap flags
tcg/ppc: Use power10 byte-reverse instructions
tcg/ppc: Support bswap flags
tcg/ppc: Split out tcg_out_bswap64
...
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/dd62bf14b756...67e25eed977c
