Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 4143f78dad42548b4c8506fafc93bedf80aaea47
https://github.com/qemu/qemu/commit/4143f78dad42548b4c8506fafc93bedf80aaea47
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Use register pair allocation for div and mulu2
Previously we hard-coded R2 and R3.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: ccbecb441ed6f7fff73fd73eead39e26a94ec045
https://github.com/qemu/qemu/commit/ccbecb441ed6f7fff73fd73eead39e26a94ec045
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Remove TCG_REG_TB
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
several follow-up patches. The primary motivation is to reduce the
less-tested code paths, pre-z10. Secondarily, this allows the
unconditional use of TCG_TARGET_HAS_direct_jump, which might be more
important for performance than any slight increase in code size.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
v4: Do not simplify tgen_ori, tgen_xori.
Commit: 6bd739ed37efb67001903cf7470b3d44c8d00683
https://github.com/qemu/qemu/commit/6bd739ed37efb67001903cf7470b3d44c8d00683
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Always set TCG_TARGET_HAS_direct_jump
Since USE_REG_TB is removed, there is no need to load the
target TB address into a register.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0a3afe09cbb0c9634ea6ae2494abbd08f01285bd
https://github.com/qemu/qemu/commit/0a3afe09cbb0c9634ea6ae2494abbd08f01285bd
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Remove USE_LONG_BRANCHES
The size of a compiled TB is limited by the uint16_t used by
gen_insn_end_off[] -- there is no need for a 32-bit branch.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 761ea522130d7beb02c6c52d0c13939e90466d31
https://github.com/qemu/qemu/commit/761ea522130d7beb02c6c52d0c13939e90466d31
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Check for long-displacement facility at startup
We are already assuming the existance of long-displacement, but were
not being explicit about it. This has been present since z990.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3e25f7da9a8e186118d23856208470fcd3ea0935
https://github.com/qemu/qemu/commit/3e25f7da9a8e186118d23856208470fcd3ea0935
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Check for extended-immediate facility at startup
The extended-immediate facility was introduced in z9-109,
which itself was end-of-life in 2017.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9c3bfb79f4bef9d5271ca59ad673d1eb7efa51db
https://github.com/qemu/qemu/commit/9c3bfb79f4bef9d5271ca59ad673d1eb7efa51db
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Check for general-instruction-extension facility at startup
The general-instruction-extension facility was introduced in z10,
which itself was end-of-life in 2019.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c68d5b7a6afab3ac1ece42bd0bd09945ca286a4e
https://github.com/qemu/qemu/commit/c68d5b7a6afab3ac1ece42bd0bd09945ca286a4e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Check for load-on-condition facility at startup
The general-instruction-extension facility was introduced in z196,
which itself was end-of-life in 2021. In addition, z196 is the
minimum CPU supported by our set of supported operating systems:
RHEL 7 (z196), SLES 12 (z196) and Ubuntu 16.04 (zEC12).
Check for facility number 45, which will be the consilidated check
for several facilities.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e62d5752f5e7fdddb6b309230589281d9fa4d609
https://github.com/qemu/qemu/commit/e62d5752f5e7fdddb6b309230589281d9fa4d609
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Remove FAST_BCR_SER facility check
The fast-bcr-serialization facility is bundled into facility 45,
along with load-on-condition. We are checking this at startup.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 238da1c942037412033a08288f73bc9815bb8c2c
https://github.com/qemu/qemu/commit/238da1c942037412033a08288f73bc9815bb8c2c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Remove DISTINCT_OPERANDS facility check
The distinct-operands facility is bundled into facility 45,
along with load-on-condition. We are checking this at startup.
Remove the a0 == a1 checks for 64-bit sub, and, or, xor, as there
is no space savings for avoiding the distinct-operands insn.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1b74cf6ea2782f4ffdecc85fdd22b2082a08502d
https://github.com/qemu/qemu/commit/1b74cf6ea2782f4ffdecc85fdd22b2082a08502d
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Use LARL+AGHI for odd addresses
Add one instead of dropping odd addresses to the constant pool.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1dd06b1aab3949a7904cd91d448d02d39b2dbf47
https://github.com/qemu/qemu/commit/1dd06b1aab3949a7904cd91d448d02d39b2dbf47
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Distinguish RRF-a and RRF-c formats
One has 3 register arguments; the other has 2 plus an m3 field.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: d84ca8046281b3ae38efac2769e821c3118e8f40
https://github.com/qemu/qemu/commit/d84ca8046281b3ae38efac2769e821c3118e8f40
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Distinguish RIE formats
There are multiple variations, with different fields.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 92c89a074cbcea660beb2259d9aa5b75f1490098
https://github.com/qemu/qemu/commit/92c89a074cbcea660beb2259d9aa5b75f1490098
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Support MIE2 multiply single instructions
The MIE2 facility adds 3-operand versions of multiply.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 668ce343f6f54d9fe900a1884b876f8008908f4d
https://github.com/qemu/qemu/commit/668ce343f6f54d9fe900a1884b876f8008908f4d
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Support MIE2 MGRK instruction
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a0332aca67772b8858d455b5b8d7f972843b3d4e
https://github.com/qemu/qemu/commit/a0332aca67772b8858d455b5b8d7f972843b3d4e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Issue XILF directly for xor_i32
There is only one instruction that is applicable
to a 32-bit immediate xor.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b2509acc60f9380ee2473074c6999dcefd9284fc
https://github.com/qemu/qemu/commit/b2509acc60f9380ee2473074c6999dcefd9284fc
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Tighten constraints for or_i64 and xor_i64
Drop support for sequential OR and XOR, as the serial dependency is
slower than loading the constant first. Let the register allocator
handle such immediates by matching only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4134083f805389f56fa9ca219c2fdadcd170e0f9
https://github.com/qemu/qemu/commit/4134083f805389f56fa9ca219c2fdadcd170e0f9
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Tighten constraints for and_i64
Let the register allocator handle such immediates by matching
only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 6c9b5c0f53dfeab2937f23c85708ae5090b435a3
https://github.com/qemu/qemu/commit/6c9b5c0f53dfeab2937f23c85708ae5090b435a3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Support MIE3 logical operations
This is andc, orc, nand, nor, eqv.
We can use nor for implementing not.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5c837bbca66805416f94cfc7acc9ad99aa3c4396
https://github.com/qemu/qemu/commit/5c837bbca66805416f94cfc7acc9ad99aa3c4396
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Create tgen_cmp2 to simplify movcond
Return both regular and inverted condition codes from tgen_cmp2.
This lets us choose after the fact which comparision we want.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 23d1394a6d1962bbbc8b5180e1a696c2895d89c8
https://github.com/qemu/qemu/commit/23d1394a6d1962bbbc8b5180e1a696c2895d89c8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Generalize movcond implementation
Generalize movcond to support pre-computed conditions, and the same
set of arguments at all times. This will be assumed by a following
patch, which needs to reuse tgen_movcond_int.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0bbf0f7acf2ba47ac549d50d2f6bc443bc27411a
https://github.com/qemu/qemu/commit/0bbf0f7acf2ba47ac549d50d2f6bc443bc27411a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Support SELGR instruction in movcond
The new select instruction provides two separate register inputs,
whereas the old load-on-condition instruction overlaps one of the
register inputs with the destination.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: bfff85184254e96abd53187f49c2624e40a34024
https://github.com/qemu/qemu/commit/bfff85184254e96abd53187f49c2624e40a34024
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Use tgen_movcond_int in tgen_clz
Reuse code from movcond to conditionally copy a2 to dest,
based on the condition codes produced by FLOGR.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 29a5ea738a20cbf8974d48a44e3a213451ded8dd
https://github.com/qemu/qemu/commit/29a5ea738a20cbf8974d48a44e3a213451ded8dd
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Implement ctpop operation
There is an older form that produces per-byte results,
and a newer form that produces per-register results.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 32c256eda68f0e75ce390d5e8e78ab6929e222ac
https://github.com/qemu/qemu/commit/32c256eda68f0e75ce390d5e8e78ab6929e222ac
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Tighten constraints for 64-bit compare
Give 64-bit comparison second operand a signed 33-bit immediate.
This is the smallest superset of uint32_t and int32_t, as used
by CLGFI and CGFI respectively. The rest of the 33-bit space
can be loaded into TCG_TMP0. Drop use of the constant pool.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 1818c71ba11682b239bbc3d891743edc0943f79f
https://github.com/qemu/qemu/commit/1818c71ba11682b239bbc3d891743edc0943f79f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Cleanup tcg_out_movi
Merge maybe_out_small_movi, as it no longer has additional users.
Use is_const_p{16,32}.
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 90497e03ca7432153c5db4a06019265486541d44
https://github.com/qemu/qemu/commit/90497e03ca7432153c5db4a06019265486541d44
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Avoid the constant pool in tcg_out_movi
Load constants in no more than two insns, which turns
out to be faster than using the constant pool.
Suggested-by: Ilya Leoshkevich <i...@linux.ibm.com>
Reviewed-by: Ilya Leoshkevich <i...@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 528d9f33cad5245c1099d77084c78bb2244d5143
https://github.com/qemu/qemu/commit/528d9f33cad5245c1099d77084c78bb2244d5143
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2023-01-08 (Sun, 08 Jan 2023)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20230106' of https://gitlab.com/rth7680/qemu into staging
tcg/s390x improvements:
- drop support for pre-z196 cpus (eol before 2017)
- add support for misc-instruction-extensions-3
- misc cleanups
# gpg: Signature made Sat 07 Jan 2023 07:47:59 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.hender...@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230106' of https://gitlab.com/rth7680/qemu: (27 commits)
tcg/s390x: Avoid the constant pool in tcg_out_movi
tcg/s390x: Cleanup tcg_out_movi
tcg/s390x: Tighten constraints for 64-bit compare
tcg/s390x: Implement ctpop operation
tcg/s390x: Use tgen_movcond_int in tgen_clz
tcg/s390x: Support SELGR instruction in movcond
tcg/s390x: Generalize movcond implementation
tcg/s390x: Create tgen_cmp2 to simplify movcond
tcg/s390x: Support MIE3 logical operations
tcg/s390x: Tighten constraints for and_i64
tcg/s390x: Tighten constraints for or_i64 and xor_i64
tcg/s390x: Issue XILF directly for xor_i32
tcg/s390x: Support MIE2 MGRK instruction
tcg/s390x: Support MIE2 multiply single instructions
tcg/s390x: Distinguish RIE formats
tcg/s390x: Distinguish RRF-a and RRF-c formats
tcg/s390x: Use LARL+AGHI for odd addresses
tcg/s390x: Remove DISTINCT_OPERANDS facility check
tcg/s390x: Remove FAST_BCR_SER facility check
tcg/s390x: Check for load-on-condition facility at startup
...
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/0ab12aa32462...528d9f33cad5
