Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 9b772b19fcccbd3d7ed12e69f272db16d023c82c
https://github.com/qemu/qemu/commit/9b772b19fcccbd3d7ed12e69f272db16d023c82c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M include/hw/intc/armv7m_nvic.h
Log Message:
-----------
hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1eb13a0947e9ef1b2ca2a3396eb661a3b22b45d1
https://github.com/qemu/qemu/commit/1eb13a0947e9ef1b2ca2a3396eb661a3b22b45d1
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: eda349be62d2c7441d9dfd5ca62b5af4db919e41
https://github.com/qemu/qemu/commit/eda349be62d2c7441d9dfd5ca62b5af4db919e41
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/internals.h
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0f150c8499e970bd079a80394ccf65bcd7a54f12
https://github.com/qemu/qemu/commit/0f150c8499e970bd079a80394ccf65bcd7a54f12
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Constify ID_PFR1 on user emulation
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: de4143fc77fd33a01b651cd00fb4f20b65de359b
https://github.com/qemu/qemu/commit/de4143fc77fd33a01b651cd00fb4f20b65de359b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M linux-user/arm/cpu_loop.c
M linux-user/user-internals.h
M target/arm/cpu.h
Log Message:
-----------
target/arm: Convert CPUARMState::eabi to boolean
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 26f08561302fdc1ba18212a5812db2f48ec9eb7b
https://github.com/qemu/qemu/commit/26f08561302fdc1ba18212a5812db2f48ec9eb7b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Avoid resetting CPUARMState::eabi field
Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1701d70e15ef7337f467d1daaecee8f6d17535aa
https://github.com/qemu/qemu/commit/1701d70e15ef7337f467d1daaecee8f6d17535aa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Restrict CPUARMState::gicv3state to sysemu
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2a94a5077637648e05b8bf3b342dadf52a4f1f7a
https://github.com/qemu/qemu/commit/2a94a5077637648e05b8bf3b342dadf52a4f1f7a
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Restrict CPUARMState::arm_boot_info to sysemu
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2bd6918f3cfe939c1335f421da2cae0221cf28e5
https://github.com/qemu/qemu/commit/2bd6918f3cfe939c1335f421da2cae0221cf28e5
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Restrict CPUARMState::nvic to sysemu
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8f4e07c9d1e8cf58ab196148e0c179e95f70201e
https://github.com/qemu/qemu/commit/8f4e07c9d1e8cf58ab196148e0c179e95f70201e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC.
Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 165876f22cd1483931a85728584b64d860329158
https://github.com/qemu/qemu/commit/165876f22cd1483931a85728584b64d860329158
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M include/hw/intc/armv7m_nvic.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu_tcg.c
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
While dozens of files include "cpu.h", only 3 files require
these NVIC helper declarations.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: dbba45e6aa1048626faabff5f6bc2b341f87166f
https://github.com/qemu/qemu/commit/dbba45e6aa1048626faabff5f6bc2b341f87166f
Author: Alex Bennée <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M tests/avocado/boot_linux.py
M tests/avocado/machine_aarch64_virt.py
Log Message:
-----------
tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
The two TCG tests for GICv2 and GICv3 are very heavy weight distros
that take a long time to boot up, especially for an --enable-debug
build. The total code coverage they give is:
Overall coverage rate:
lines......: 11.2% (59584 of 530123 lines)
functions..: 15.0% (7436 of 49443 functions)
branches...: 6.3% (19273 of 303933 branches)
We already get pretty close to that with the machine_aarch64_virt
tests which only does one full boot (~120s vs ~600s) of alpine. We
expand the kernel+initrd boot (~8s) to test both GICs and also add an
RNG device and a block device to generate a few IRQs and exercise the
storage layer. With that we get to a coverage of:
Overall coverage rate:
lines......: 11.0% (58121 of 530123 lines)
functions..: 14.9% (7343 of 49443 functions)
branches...: 6.0% (18269 of 303933 branches)
which I feel is close enough given the massive time saving. If we want
to target any more sub-systems we can use lighter weight more directed
tests.
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Acked-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Cc: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: c2ecb424fb15ba0db0d9445721e6e8a8e79c4976
https://github.com/qemu/qemu/commit/c2ecb424fb15ba0db0d9445721e6e8a8e79c4976
Author: Mostafa Saleh <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3: Add GBPA register
GBPA register can be used to globally abort all
transactions.
It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).
Other fields have default values of Use Incoming.
If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.
Signed-off-by: Mostafa Saleh <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: f4880c2da4c8eadfee3f40b76af77f77574cebef
https://github.com/qemu/qemu/commit/f4880c2da4c8eadfee3f40b76af77f77574cebef
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/Kconfig
Log Message:
-----------
hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
a QEMU configured using --without-default-devices, we get:
$ qemu-system-aarch64 -M xlnx-zcu102
qemu-system-aarch64: missing object type 'usb_dwc3'
Abort trap: 6
Fix by adding the missing Kconfig dependency.
Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Reviewed-by: Francisco Iglesias <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8e4f2b277b4c1e1460a22e16e59fa11e6c36fcf4
https://github.com/qemu/qemu/commit/8e4f2b277b4c1e1460a22e16e59fa11e6c36fcf4
Author: Cornelia Huck <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
arm/virt: don't try to spell out the accelerator
Just use current_accel_name() directly.
Signed-off-by: Cornelia Huck <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 73c793dab2d3dd07a0b6c9312d645863ca46c128
https://github.com/qemu/qemu/commit/73c793dab2d3dd07a0b6c9312d645863ca46c128
Author: Hao Wu <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself to maintainers and remove Havard
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu <[email protected]>
Acked-by: Havard Skinnemoen <[email protected]>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 69fbfb8ff1369bd51ada1b4fb9b800e3e8d92fba
https://github.com/qemu/qemu/commit/69fbfb8ff1369bd51ada1b4fb9b800e3e8d92fba
Author: Hao Wu <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M MAINTAINERS
M hw/ssi/meson.build
A hw/ssi/npcm_pspi.c
M hw/ssi/trace-events
A include/hw/ssi/npcm_pspi.h
Log Message:
-----------
hw/ssi: Add Nuvoton PSPI Module
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Chris Rauer <[email protected]>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4d120d7d6084ef388a9016d7dbf091c4d5e055fc
https://github.com/qemu/qemu/commit/4d120d7d6084ef388a9016d7dbf091c4d5e055fc
Author: Hao Wu <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm7xx.c
M include/hw/arm/npcm7xx.h
Log Message:
-----------
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Titus Rwantare <[email protected]>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ca3fbed896ec867ea0826b9859c6636ca927e835
https://github.com/qemu/qemu/commit/ca3fbed896ec867ea0826b9859c6636ca927e835
Author: Jean-Philippe Brucker <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/smmu-common.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Support 64-bit addresses
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Jean-Philippe Brucker <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e431b8f608d22b0bca64b75b8738b2a6ab4468bd
https://github.com/qemu/qemu/commit/e431b8f608d22b0bca64b75b8738b2a6ab4468bd
Author: Jean-Philippe Brucker <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm/smmu-common: Fix TTB1 handling
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.
Reported-by: Ola Hugosson <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Jean-Philippe Brucker <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a06e3a68ba2b0f51d28f83e94f8266811c0ba05c
https://github.com/qemu/qemu/commit/a06e3a68ba2b0f51d28f83e94f8266811c0ba05c
Author: Claudio Fontana <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: rename handle_semihosting to tcg_handle_semihosting
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0c1aaa66c248b7375112a2d6f5ca3bafaeda0aa5
https://github.com/qemu/qemu/commit/0c1aaa66c248b7375112a2d6f5ca3bafaeda0aa5
Author: Claudio Fontana <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: wrap psci call with tcg_enabled
for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: d55b2a2aa37ab07eed1517791344392b3c147f09
https://github.com/qemu/qemu/commit/d55b2a2aa37ab07eed1517791344392b3c147f09
Author: Claudio Fontana <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
Signed-off-by: Claudio Fontana <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 501e6d1f6c75e9bc844098fd13fca730188056ef
https://github.com/qemu/qemu/commit/501e6d1f6c75e9bc844098fd13fca730188056ef
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9200d5cc749fe06c52da395d94f39aaa5c380635
https://github.com/qemu/qemu/commit/9200d5cc749fe06c52da395d94f39aaa5c380635
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move cpregs code out of cpu.h
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.
Code moved verbatim.
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5ad2d7a97cd9d1ed2527d888d343ee40f1b871f3
https://github.com/qemu/qemu/commit/5ad2d7a97cd9d1ed2527d888d343ee40f1b871f3
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M tests/avocado/avocado_qemu/__init__.py
Log Message:
-----------
tests/avocado: Skip tests that require a missing accelerator
If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.
We can now write tests without explicit calls to require_accelerator,
just the tag is enough.
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9bb9a3f3c80d57ef2abed12253a613315fd8be85
https://github.com/qemu/qemu/commit/9bb9a3f3c80d57ef2abed12253a613315fd8be85
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M tests/avocado/boot_linux_console.py
M tests/avocado/reverse_debugging.py
Log Message:
-----------
tests/avocado: Tag TCG tests with accel:tcg
This allows the test to be skipped when TCG is not present in the QEMU
binary.
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6c8a108dea3a79a8003e2783d984591c411714e4
https://github.com/qemu/qemu/commit/6c8a108dea3a79a8003e2783d984591c411714e4
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
target/arm: Use "max" as default cpu for the virt machine with KVM
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed-off-by: Fabiano Rosas <[email protected]>
Acked-by: Richard Henderson <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 500a0accb5319df02c0385f877a37f7e2a2a0bb3
https://github.com/qemu/qemu/commit/500a0accb5319df02c0385f877a37f7e2a2a0bb3
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M tests/qtest/arm-cpu-features.c
Log Message:
-----------
tests/qtest: arm-cpu-features: Match tests to required accelerators
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Acked-by: Thomas Huth <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8
https://github.com/qemu/qemu/commit/caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8
Author: Fabiano Rosas <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
These tests set -accel tcg, so restrict them to when TCG is present.
Signed-off-by: Fabiano Rosas <[email protected]>
Acked-by: Richard Henderson <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: d8d20b38ec5875b98cfdae52c1f2132540cd65b5
https://github.com/qemu/qemu/commit/d8d20b38ec5875b98cfdae52c1f2132540cd65b5
Author: Peter Maydell <[email protected]>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M MAINTAINERS
M docs/system/arm/nuvoton.rst
M hw/arm/Kconfig
M hw/arm/npcm7xx.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/intc/armv7m_nvic.c
M hw/ssi/meson.build
A hw/ssi/npcm_pspi.c
M hw/ssi/trace-events
M include/hw/arm/npcm7xx.h
M include/hw/arm/smmu-common.h
M include/hw/arm/smmuv3.h
M include/hw/intc/armv7m_nvic.h
A include/hw/ssi/npcm_pspi.h
M linux-user/arm/cpu_loop.c
M linux-user/user-internals.h
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/m_helper.c
M target/arm/machine.c
M tests/avocado/avocado_qemu/__init__.py
M tests/avocado/boot_linux.py
M tests/avocado/boot_linux_console.py
M tests/avocado/machine_aarch64_virt.py
M tests/avocado/reverse_debugging.py
M tests/qtest/arm-cpu-features.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-target-arm-20230216' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Some mostly M-profile-related code cleanups
* avocado: Retire the boot_linux.py AArch64 TCG tests
* hw/arm/smmuv3: Add GBPA register
* arm/virt: don't try to spell out the accelerator
* hw/arm: Attach PSPI module to NPCM7XX SoC
* Some cleanup/refactoring patches aiming towards
allowing building Arm targets without CONFIG_TCG
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# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>"
[ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
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* tag 'pull-target-arm-20230216' of
https://git.linaro.org/people/pmaydell/qemu-arm: (30 commits)
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
tests/qtest: arm-cpu-features: Match tests to required accelerators
target/arm: Use "max" as default cpu for the virt machine with KVM
tests/avocado: Tag TCG tests with accel:tcg
tests/avocado: Skip tests that require a missing accelerator
target/arm: Move cpregs code out of cpu.h
target/arm: Move PC alignment check
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
target/arm: wrap psci call with tcg_enabled
target/arm: rename handle_semihosting to tcg_handle_semihosting
hw/arm/smmu-common: Fix TTB1 handling
hw/arm/smmu-common: Support 64-bit addresses
hw/arm: Attach PSPI module to NPCM7XX SoC
hw/ssi: Add Nuvoton PSPI Module
MAINTAINERS: Add myself to maintainers and remove Havard
arm/virt: don't try to spell out the accelerator
hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
hw/arm/smmuv3: Add GBPA register
tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/6dffbe36af79...d8d20b38ec58
