Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 981562ed2baaa28067b7ba77fb579d0878782000
https://github.com/qemu/qemu/commit/981562ed2baaa28067b7ba77fb579d0878782000
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/gdbstub.c
Log Message:
-----------
target/ppc: gdbstub init spr gdb_id for all CPUs
Make sure each CPU gets its state set up for gdb, not just the ones
before PowerPCCPUClass has had its gdb state set up.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b08e8a837ec91fc8dd84aa487876b9f244fc2677
https://github.com/qemu/qemu/commit/b08e8a837ec91fc8dd84aa487876b9f244fc2677
Author: Joel Stanley <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
ppc/pnv/pci: Clean up error messages
The phb error macros add a newline for you, so remove the second one to
avoid double whitespace.
Signed-off-by: Joel Stanley <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 602b88ec8a204cc44821217c0ceff5a395cf820b
https://github.com/qemu/qemu/commit/602b88ec8a204cc44821217c0ceff5a395cf820b
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add reviewers for PowerNV baremetal emulation
Fred and Nick have been hacking baremetal POWER systems (OPAL) for
many years. They use and modify the QEMU models regularly. Add them as
PowerNV reviewers.
Cc: Frédéric Barrat <[email protected]>
Cc: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Frederic Barrat <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 58fc20f0e384177e78346630cdf8c72f538d167e
https://github.com/qemu/qemu/commit/58fc20f0e384177e78346630cdf8c72f538d167e
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add reviewer for PowerPC TCG CPUs
Nick has great knowledge of the PowerPC CPUs, software and hardware.
Add him as a reviewer on CPU TCG modeling.
Cc: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 4901a34d26a686d41647d34b04a4e0c6ea81bd6f
https://github.com/qemu/qemu/commit/4901a34d26a686d41647d34b04a4e0c6ea81bd6f
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add reviewer for XIVE
Fred discusses frequently with the IBM HW designers, he is fluent in
XIVE logic, add him as a reviewer.
Cc: Frédéric Barrat <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Frederic Barrat <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9df480db3bb89152821a74b28c8fb385956702a1
https://github.com/qemu/qemu/commit/9df480db3bb89152821a74b28c8fb385956702a1
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
ppc/prep: Report an error when run with KVM
The 'prep' machine never supported KVM. This piece of code was
probably inherited from another model.
Cc: Hervé Poussineau <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 74b2fd630761b3e3fe39a5314fcec04829060502
https://github.com/qemu/qemu/commit/74b2fd630761b3e3fe39a5314fcec04829060502
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/ppc440_bamboo.c
Log Message:
-----------
ppc/bamboo: Report an error when run with KVM
The 'bamboo' machine was used as a KVM platform in the early days (~2008).
It clearly doesn't support it anymore.
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 518f72ec4bb395647921d5091d85c7335c3968ac
https://github.com/qemu/qemu/commit/518f72ec4bb395647921d5091d85c7335c3968ac
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Rephrase error when run with KVM
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c4550e6e9824c3fb5ee980cc8c9b175b8baf3d1a
https://github.com/qemu/qemu/commit/c4550e6e9824c3fb5ee980cc8c9b175b8baf3d1a
Author: Cédric Le Goater <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Fix timer register accessors when !KVM
When the Timer Control and Timer Status registers are modified, avoid
calling the KVM backend when not available
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cb2f6c3d69ea5b5bdc37c8330266ab67db629fc5
https://github.com/qemu/qemu/commit/cb2f6c3d69ea5b5bdc37c8330266ab67db629fc5
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
ppc/spapr: H_ENTER_NESTED should restore host XER ca field
Fix missing env->ca restore when going from L2 back to the host.
Fixes: 120f738a467 ("spapr: implement nested-hv capability for the virtual
hypervisor")
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c709e8eacd5578f84c0dffbfe65a743a281d1d46
https://github.com/qemu/qemu/commit/c709e8eacd5578f84c0dffbfe65a743a281d1d46
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr_cpu_core.h
Log Message:
-----------
ppc/spapr: Add a nested state struct
Rather than use a copy of CPUPPCState to store the host state while
the environment has been switched to the L2, use a new struct for
this purpose.
Have helper functions to save and load this host state.
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cb4e61a33b7585642a8a7ff9e5b3b78599bcc582
https://github.com/qemu/qemu/commit/cb4e61a33b7585642a8a7ff9e5b3b78599bcc582
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
ppc/spapr: load and store l2 state with helper functions
Arguably this is just shuffling around register accesses, but one nice
thing it does is allow the exit to save away the L2 state then switch
the environment to the L1 before copying L2 data back to the L1, which
logically flows more naturally and simplifies the error paths.
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6b8a05373bf142fe5fd3839c3675da005bfc9b49
https://github.com/qemu/qemu/commit/6b8a05373bf142fe5fd3839c3675da005bfc9b49
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/meson.build
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_nested.c
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_nested.h
Log Message:
-----------
ppc/spapr: Move spapr nested HV to a new file
Create spapr_nested.c for most of the nested HV implementation.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 888050cf519eb5995424cf415f4f8f269de96824
https://github.com/qemu/qemu/commit/888050cf519eb5995424cf415f4f8f269de96824
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix instruction loading endianness in alignment interrupt
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 74574c3845a046174993092cdc3c03f481dc2cf3
https://github.com/qemu/qemu/commit/74574c3845a046174993092cdc3c03f481dc2cf3
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Change partition-scope translate interface
Rather than always performing partition scope page table translation
with access type of 0 (MMU_DATA_LOAD), pass through the processor
access type which first initiated the translation sequence. Process-
scoped page table loads are then set to MMU_DATA_LOAD access type in
the xlate function.
This will allow more information to be passed to the exception
handler in the next patch.
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5a5d3b23cb281d99ee6dd74afa41864428e35241
https://github.com/qemu/qemu/commit/5a5d3b23cb281d99ee6dd74afa41864428e35241
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Add SRR1 prefix indication to interrupt handlers
ISA v3.1 introduced prefix instructions. Among the changes, various
synchronous interrupts report whether they were caused by a prefix
instruction in (H)SRR1.
The case of instruction fetch that causes an HDSI due to access of a
process-scoped table faulting on the partition scoped translation is the
tricky one. As with ISIs and HISIs, this does not try to set the prefix
bit because there is no instruction image to be loaded. The HDSI needs
the originating access type to be passed through to the handler to
distinguish this from HDSIs that fault translating process scoped tables
originating from a load or store instruction (in that case the prefix
bit should be provided).
Reviewed-by: Fabiano Rosas <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
[ clg: checkpatch issues ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a3c020d85ea721fc2a57b28f305a532b2c388f7c
https://github.com/qemu/qemu/commit/a3c020d85ea721fc2a57b28f305a532b2c388f7c
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Implement HEIR SPR
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Only TCG raises HEAI interrupts so this can be made TCG-only.
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: eb701f30120d899bdaa202c3cbd9219055fccae0
https://github.com/qemu/qemu/commit/eb701f30120d899bdaa202c3cbd9219055fccae0
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 488aad116651f9838767fd53d5660e6702925c14
https://github.com/qemu/qemu/commit/488aad116651f9838767fd53d5660e6702925c14
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Better CTRL SPR implementation
The CTRL register is able to write the bit in the RUN field, which gets
reflected into the TS field which is read-only and contains the state of
the RUN field for all threads in the core.
TCG does not implement SMT, so the correct implementation just requires
mirroring the RUN bit into the first bit of the TS field.
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 984eda58f20763ffb56b7aff34ad60bdeb118eb1
https://github.com/qemu/qemu/commit/984eda58f20763ffb56b7aff34ad60bdeb118eb1
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Fix sc instruction handling of LEV field
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the instruction execution to just set lev from the low bit
of the field. Processors which don't support the LEV field will continue
to ignore it.
ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall
instruction. TCG does not support Ultravisor, so don't worry about
that bit.
Suggested-by: "Harsh Prateek Bora" <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b769d4c8f4c67e794444a6376b849db2caeeff3e
https://github.com/qemu/qemu/commit/b769d4c8f4c67e794444a6376b849db2caeeff3e
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add initial flags and helpers for SMT support
TGC SMT emulation needs to know whether it is running with SMT siblings,
to be able to iterate over siblings in a core, and to serialise
threads to access per-core shared SPRs. Add infrastructure to do these
things.
For now the sibling iteration and serialisation are implemented in a
simple but inefficient way. SMT shared state and sibling access is not
too common, and SMT configurations are mainly useful to test system
code, so performance is not to critical.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[ clg: fix build breakage with clang ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c5d98a7b3d455204e24212cb769dec8f490e4e1c
https://github.com/qemu/qemu/commit/c5d98a7b3d455204e24212cb769dec8f490e4e1c
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M target/ppc/helper.h
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d24e80b2ae3e061a200178d679711b5538479a72
https://github.com/qemu/qemu/commit/d24e80b2ae3e061a200178d679711b5538479a72
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
M target/ppc/excp_helper.c
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add msgsnd/p and DPDES SMT support
Doorbells in SMT need to coordinate msgsnd/msgclr and DPDES access from
multiple threads that affect the same state.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 516cd737330a9b4d90a66136ebf738c4653b4e78
https://github.com/qemu/qemu/commit/516cd737330a9b4d90a66136ebf738c4653b4e78
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled()
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can not assume that
'!kvm == tcg', so test for the correct accelerator. This
also eases code review, because here we don't care about
KVM, we really want to test for TCG.
Reviewed-by: Greg Kurz <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: David Gibson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
[np: Fix changelog typo noticed by Zoltan]
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: dc5e072188ea622071bab47c4f899817d6ef1295
https://github.com/qemu/qemu/commit/dc5e072188ea622071bab47c4f899817d6ef1295
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
spapr's nested-HV capability does not currently coexist with SMT, so
that combination is prohibited (interestingly somewhat analogous to
LPAR-per-core mode on real hardware which also does not support KVM).
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[ clg: Also test smp_threads when checking for POWER8 CPU and above ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8f4c627b2f1479c15822ab2123ff4bdd63c24417
https://github.com/qemu/qemu/commit/8f4c627b2f1479c15822ab2123ff4bdd63c24417
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M tests/avocado/ppc_pseries.py
Log Message:
-----------
tests/avocado: boot ppc64 pseries to Linux VFS mount
This machine can boot Linux to VFS mount, so don't stop in early boot.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 242e8b4dca60574a81c92ba4b8bcb538550c6cfc
https://github.com/qemu/qemu/commit/242e8b4dca60574a81c92ba4b8bcb538550c6cfc
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M tests/avocado/ppc_pseries.py
Log Message:
-----------
tests/avocado: Add ppc64 pseries multiprocessor boot tests
Add mult-thread/core/socket Linux boot tests that ensure the right
topology comes up. Of particular note is a SMT test, which is a new
capability for TCG.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2a24e6e394c0badefd1c6b1ecf571f3663236300
https://github.com/qemu/qemu/commit/2a24e6e394c0badefd1c6b1ecf571f3663236300
Author: Frederic Barrat <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/pnv_xive2.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
pnv/xive2: Add a get_config() method on the presenter class
The presenters for xive on P9 and P10 are mostly similar but the
behavior can be tuned through a few CQ registers. This patch adds a
"get_config" method, which will allow to access that config from the
presenter in a later patch.
For now, just define the config for the TIMA version.
Signed-off-by: Frederic Barrat <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 177835304b39b6ed6a7c51fd19263ac10995dbec
https://github.com/qemu/qemu/commit/177835304b39b6ed6a7c51fd19263ac10995dbec
Author: Frederic Barrat <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/xive.c
Log Message:
-----------
pnv/xive2: Check TIMA special ops against a dedicated array for P10
Accessing the TIMA from some specific ring/offset combination can
trigger a special operation, with or without side effects. It is
implemented in qemu with an array of special operations to compare
accesses against. Since the presenter on P10 is pretty similar to P9,
we had the full array defined for P9 and we just had a special case
for P10 to treat one access differently. With a recent change,
6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports"), we
now ignore some of the bits of the TIMA address, but that patch
managed to botch the detection of the special case for P10.
To clean that up, this patch introduces a full array of special ops to
be used for P10. The code to detect a special access is common with
P9, only the array of operations differs. The presenter can pick the
correct array of special ops based on its configuration introduced in
a previous patch.
Fixes: Coverity CID 1512997, 1512998
Fixes: 6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports")
Signed-off-by: Frederic Barrat <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5eb63b88d0ac259c2f49e62b6dcc6527a5caf255
https://github.com/qemu/qemu/commit/5eb63b88d0ac259c2f49e62b6dcc6527a5caf255
Author: Nicholas Piggin <[email protected]>
Date: 2023-06-25 (Sun, 25 Jun 2023)
Changed paths:
M tests/avocado/ppc_pseries.py
Log Message:
-----------
tests/avocado: ppc test VOF bios Linux boot
VOF is the new lightweight fast pseries bios. Add a Linux boot test
using VOF.
More tests could be moved to use VOF becasue it's much faster, but
just dip one toe in the water first here. SLOF should continue to be
tested too.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f9925abbda1c324d901d8e7fe63bad09a35ae740
https://github.com/qemu/qemu/commit/f9925abbda1c324d901d8e7fe63bad09a35ae740
Author: Richard Henderson <[email protected]>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M MAINTAINERS
M hw/intc/pnv_xive.c
M hw/intc/pnv_xive2.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M hw/pci-host/pnv_phb4.c
M hw/ppc/meson.build
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/prep.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_nested.c
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
A include/hw/ppc/spapr_nested.h
M include/hw/ppc/xive.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/gdbstub.c
M target/ppc/helper.h
M target/ppc/kvm.c
M target/ppc/misc_helper.c
M target/ppc/mmu-radix64.c
M target/ppc/translate.c
M tests/avocado/ppc_pseries.py
Log Message:
-----------
Merge tag 'pull-ppc-20230626' of https://github.com/legoater/qemu into staging
ppc queue:
* New maintainers
* Nested implementation cleanups
* Various cleanups of the CPU implementation
* SMT support for pseries
* Improvements of the XIVE2 TIMA modeling
* Extra avocado tests for pseries
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# gpg: Good signature from "Cédric Le Goater <[email protected]>" [undefined]
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# gpg: There is no indication that the signature belongs to the owner.
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* tag 'pull-ppc-20230626' of https://github.com/legoater/qemu: (30 commits)
tests/avocado: ppc test VOF bios Linux boot
pnv/xive2: Check TIMA special ops against a dedicated array for P10
pnv/xive2: Add a get_config() method on the presenter class
tests/avocado: Add ppc64 pseries multiprocessor boot tests
tests/avocado: boot ppc64 pseries to Linux VFS mount
spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs
hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled()
target/ppc: Add msgsnd/p and DPDES SMT support
target/ppc: Add support for SMT CTRL register
target/ppc: Add initial flags and helpers for SMT support
target/ppc: Fix sc instruction handling of LEV field
target/ppc: Better CTRL SPR implementation
target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts
target/ppc: Implement HEIR SPR
target/ppc: Add SRR1 prefix indication to interrupt handlers
target/ppc: Change partition-scope translate interface
target/ppc: Fix instruction loading endianness in alignment interrupt
ppc/spapr: Move spapr nested HV to a new file
ppc/spapr: load and store l2 state with helper functions
ppc/spapr: Add a nested state struct
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/79dbd910c9ea...f9925abbda1c
