Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0a8d4f2cfcedfbfaef32f87b111d8311fb2f2275
https://github.com/qemu/qemu/commit/0a8d4f2cfcedfbfaef32f87b111d8311fb2f2275
Author: Ani Sinha <[email protected]>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M tests/avocado/acpi-bits.py
Log Message:
-----------
acpi/tests/avocado/bits: wait for 200 seconds for SHUTDOWN event from bits VM
By default, the timeout to receive any specified event from the QEMU VM is 60
seconds set by the python avocado test framework. Please see event_wait() and
events_wait() in python/qemu/machine/machine.py. If the matching event is not
triggered within that interval, an asyncio.TimeoutError is generated. Since the
timeout for the bits avocado test is 200 secs, we need to make event_wait()
timeout of the same value as well so that an early timeout is not triggered by
the avocado framework.
CC: [email protected]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2077
Signed-off-by: Ani Sinha <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: dc3982c05b38b1bed5be13f852b3a2568ed6a286
https://github.com/qemu/qemu/commit/dc3982c05b38b1bed5be13f852b3a2568ed6a286
Author: Peter Maydell <[email protected]>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M meson.build
M tests/qtest/meson.build
M tests/qtest/npcm7xx_watchdog_timer-test.c
Log Message:
-----------
Merge tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu into
staging
* Improve the timeouts for some problematic qtests
* Enable some ROP mitigation compiler switches
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# gpg: Signature made Tue 16 Jan 2024 07:45:57 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "[email protected]"
# gpg: Good signature from "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu:
meson: mitigate against use of uninitialize stack for exploits
meson: mitigate against ROP exploits with -fzero-call-used-regs
qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes
tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default
tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes
Signed-off-by: Peter Maydell <[email protected]>
Commit: a6f9c18743d20b7deffff2deb2a9e6c029544198
https://github.com/qemu/qemu/commit/a6f9c18743d20b7deffff2deb2a9e6c029544198
Author: Peter Maydell <[email protected]>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/plugin-helpers.h
M contrib/plugins/execlog.c
M docs/devel/tcg-plugins.rst
M gdbstub/gdbstub.c
M hw/core/cpu-common.c
M hw/riscv/boot.c
M include/exec/gdbstub.h
M include/hw/core/cpu.h
M include/qemu/plugin.h
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/qemu-plugins.symbols
M scripts/feature_to_c.py
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/loongarch/gdbstub.c
M target/m68k/cpu.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/gdbstub.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/gdbstub.c
Log Message:
-----------
Merge tag 'pull-registers-for-plugins-160124-2' of
https://gitlab.com/stsquad/qemu into staging
read-only register access for plugins:
- move misa_mxl to CPU class for riscv
- use GDBFeature for arm XML
- use GDBFeature for ppc XML
- use GDBFeature for riscv XML
- unify gdb code to use GDBFeature
- move dynamic XML generation to core GDB code
- provide introspection APIs for rest of QEMU
- expose a plugin API to access registers
- fix memory re-use in execlog
- extend execlog to track registers
- optimise instrumentation based on disassembly
- tweak API docs and expand on assumptions
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# gpg: Signature made Tue 16 Jan 2024 10:35:27 GMT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key)
<[email protected]>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-registers-for-plugins-160124-2' of https://gitlab.com/stsquad/qemu:
(22 commits)
docs/devel: document some plugin assumptions
docs/devel: lift example and plugin API sections up
contrib/plugins: optimise the register value tracking
contrib/plugins: extend execlog to track register changes
contrib/plugins: fix imatch
plugins: add an API to read registers
gdbstub: expose api to find registers
plugins: Use different helpers when reading registers
gdbstub: Add members to identify registers to GDBFeature
hw/core/cpu: Remove gdb_get_dynamic_xml member
gdbstub: Infer number of core registers from XML
gdbstub: Simplify XML lookup
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
gdbstub: Use GDBFeature for GDBRegisterState
gdbstub: Use GDBFeature for gdb_register_coprocessor
target/riscv: Use GDBFeature for dynamic XML
target/ppc: Use GDBFeature for dynamic XML
target/arm: Use GDBFeature for dynamic XML
target/riscv: Validate misa_mxl_max only once
target/riscv: Move misa_mxl_max to class
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/9c693df15f24...a6f9c18743d2
