Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 869020451b3ab50bf825204a89adc1ee76ffb2ab
https://github.com/qemu/qemu/commit/869020451b3ab50bf825204a89adc1ee76ffb2ab
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/display/vga.c
Log Message:
-----------
vga: merge conditionals on shift control register
There are two sets of conditionals using the shift control bits: one to
verify the palette and adjust disp_width, one to compute the "v" and
"bits" variables. Merge them into one, with the extra benefit that
we now have the "bits" value available early and can use it to
compute region_end.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 30ed333404def8d93c54618f2cc850bc8f16dd2b
https://github.com/qemu/qemu/commit/30ed333404def8d93c54618f2cc850bc8f16dd2b
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/display/vga.c
Log Message:
-----------
vga: move computation of dirty memory region later
Move the computation of region_start and region_end after the value of
"bits" is known. This makes it possible to distinguish modes that
support horizontal pel panning from modes that do not.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: bae34170a758665682333a32846404af97e7c6c0
https://github.com/qemu/qemu/commit/bae34170a758665682333a32846404af97e7c6c0
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/display/vga.c
Log Message:
-----------
vga: adjust dirty memory region if pel panning is active
When pel panning is active, one more byte is read from each of the VGA
memory planes. This has to be accounted in the computation of region_end,
otherwise vga_draw_graphic() fails an assertion:
qemu-system-i386: ../system/physmem.c:946:
cpu_physical_memory_snapshot_get_dirty: Assertion `start + length <= snap->end'
failed.
Reported-by: Helge Konetzka <[email protected]>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2244
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 8ace17ded861191a8d68eb2ba88a1d102de794a9
https://github.com/qemu/qemu/commit/8ace17ded861191a8d68eb2ba88a1d102de794a9
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/display/vga.c
Log Message:
-----------
vga: do not treat horiz pel panning value of 8 as "enabled"
Horizontal pel panning bit 3 is only used in text mode. In graphics
mode, it can be treated as if it was zero, thus not extending the
dirty memory region.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: c1457e87fcb8d96bd2d731b554ba1520b7347498
https://github.com/qemu/qemu/commit/c1457e87fcb8d96bd2d731b554ba1520b7347498
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/scsi/lsi53c895a.c
Log Message:
-----------
lsi53c895a: avoid out of bounds access to s->msg[]
If no bytes are there to process in the message in phase,
the input data latch (s->sidl) is set to s->msg[-1]. Just
do nothing since no DMA is performed.
Reported-by: Chuhong Yuan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: bc376ff802e2886e60e28c8bc7bb2851aea643ef
https://github.com/qemu/qemu/commit/bc376ff802e2886e60e28c8bc7bb2851aea643ef
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/scsi/lsi53c895a.c
Log Message:
-----------
lsi53c895a: detect invalid Block Move instruction
The spec for the lsi53c895a says: "If the instruction is a Block Move
and a value of 0x000000 is loaded into the DBC register, an illegal
instruction interrupt occurs if the LSI53C895A is not in target mode,
Command phase".
Because QEMU only operates in initiator mode, generate the interrupt
unconditionally if the low 24 bits are 0x000000.
Reported-by: Chuhong Yuan <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: eac4af186f6db46fc90ec571a855bd6fa4cb7841
https://github.com/qemu/qemu/commit/eac4af186f6db46fc90ec571a855bd6fa4cb7841
Author: Paolo Bonzini <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
pc_q35: remove unnecessary m->alias assignment
The assignment is already inherited from pc-q35-8.2.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1689c8589def73159910e98b4944fde26b8f8081
https://github.com/qemu/qemu/commit/1689c8589def73159910e98b4944fde26b8f8081
Author: Peter Maydell <[email protected]>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/display/vga.c
M hw/i386/pc_q35.c
M hw/scsi/lsi53c895a.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* lsi53c895a: fix assertion failure with invalid Block Move
* vga: fix assertion failure with 4- and 16-color modes
* remove unnecessary assignment
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# gpg: Good signature from "Paolo Bonzini <[email protected]>" [full]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
pc_q35: remove unnecessary m->alias assignment
lsi53c895a: detect invalid Block Move instruction
lsi53c895a: avoid out of bounds access to s->msg[]
vga: do not treat horiz pel panning value of 8 as "enabled"
vga: adjust dirty memory region if pel panning is active
vga: move computation of dirty memory region later
vga: merge conditionals on shift control register
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/2fd8df9362d7...1689c8589def
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