Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 6b568e3f1dc22e839cd56b47e22c2aa5ece21367
https://github.com/qemu/qemu/commit/6b568e3f1dc22e839cd56b47e22c2aa5ece21367
Author: Thomas Huth <th...@redhat.com>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M qom/object.c
M target/sparc/cpu.c
Log Message:
-----------
target/sparc/cpu: Rename the CPU models with a "+" in their names
Commit b447378e12 ("qom/object: Limit type names to alphanumerical ...")
cut down the amount of allowed characters for QOM types to a saner set.
The "+" character was meant to be included in this set, so we had to
add a hack there to still allow the legacy names of POWER and Sparc64
CPUs. However, instead of putting such a hack in the common QOM code,
there is a much better place to do this: The sparc_cpu_class_by_name()
function which is used to look up the names of all Sparc CPUs.
Thus let's finally get rid of the "+" in the Sparc CPU names, and provide
backward compatibility for the old names via some simple checks in the
sparc_cpu_class_by_name() function.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240419084812.504779-2-th...@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 4a7bdec3a6f3f6d9f75715e420a4c826135a1065
https://github.com/qemu/qemu/commit/4a7bdec3a6f3f6d9f75715e420a4c826135a1065
Author: Thomas Huth <th...@redhat.com>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc/cpu: Avoid spaces by default in the CPU names
The output of "-cpu help" is currently rather confusing to the users:
It might not be fully clear which part of the output defines the CPU
names since the CPU names contain white spaces (which we later have to
convert into dashes internally). At best it's at least a nuisance since
the users might need to specify the CPU names with quoting on the command
line if they are not aware of the fact that the CPU names could be written
with dashes instead. So let's finally clean up this mess by using dashes
instead of white spaces for the CPU names, like we're doing it internally
later (and like we're doing it in most other targets of QEMU).
Note that it is still possible to pass the CPU names with spaces to the
"-cpu" option, since sparc_cpu_type_name() still translates those to "-".
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-Id: <20240419084812.504779-3-th...@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 49ce37e3d024260072bdfa4c5569859d1f338cb2
https://github.com/qemu/qemu/commit/49ce37e3d024260072bdfa4c5569859d1f338cb2
Author: Thomas Huth <th...@redhat.com>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M docs/system/target-sparc.rst
Log Message:
-----------
docs/system/target-sparc: Improve the Sparc documentation
Add some words about how to enable or disable boolean features,
and remove the note about a Linux kernel being available on the
QEMU website (they have been removed long ago already), and the
note about NetBSD and OpenBSD still having issues (they should
work fine nowadays).
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141
Signed-off-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240419084812.504779-4-th...@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 029171b5d62fe11a0dce52f64efb356f7fea144d
https://github.com/qemu/qemu/commit/029171b5d62fe11a0dce52f64efb356f7fea144d
Author: Thomas Huth <th...@redhat.com>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+"
For consistency we should drop the names with a "+" in it in the
long run.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240419084812.504779-5-th...@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 7c420a4d7c080002018af20aed56ceb0bf81ad43
https://github.com/qemu/qemu/commit/7c420a4d7c080002018af20aed56ceb0bf81ad43
Author: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M hw/sparc64/sun4u.c
Log Message:
-----------
hw/sparc64: set iommu_platform=on for virtio devices attached to the sun4u
machine
The sun4u machine has an IOMMU and therefore it is possible to program it such
that the virtio-device IOVA does not map directly to the CPU physical address.
This is not a problem with Linux which always maps the IOVA directly to the CPU
physical address, however it is required for the NetBSD virtio driver where this
is not the case.
Set the sun4u machine defaults for all virtio devices so that disable-legacy=on
and iommu_platform=on to ensure a default configuration will allow virtio
devices to function correctly on both Linux and NetBSD.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Message-Id: <20240418205730.31396-1-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 1cde1a2a89e7c6ac1c8240b09f9b3d066cd01270
https://github.com/qemu/qemu/commit/1cde1a2a89e7c6ac1c8240b09f9b3d066cd01270
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/sparc: Add more hwcap bits for sparc64
Supply HWCAP_SPARC_V8PLUS, HWCAP_SPARC_MUL32, HWCAP_SPARC_DIV32,
HWCAP_SPARC_POPC, HWCAP_SPARC_FSMULD, HWCAP_SPARC_VIS, HWCAP_SPARC_VIS2.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240502165528.244004-2-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 7b616f36de0bde126e1ba6b0793ed26fc414a1ff
https://github.com/qemu/qemu/commit/7b616f36de0bde126e1ba6b0793ed26fc414a1ff
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix FEXPAND
This is a 2-operand instruction, not 3-operand.
Worse, we took the source from the wrong operand.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20240502165528.244004-3-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 9157dccc7e71f7c94581c38f38acbef9a21bbe9a
https://github.com/qemu/qemu/commit/9157dccc7e71f7c94581c38f38acbef9a21bbe9a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix FMUL8x16
This instruction has f32 as source1, which alters the
decoding of the register number, which means we've been
passing the wrong data for odd register numbers.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20240502165528.244004-4-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: a859602c746baf4892cc8ca1ce003e92411d1716
https://github.com/qemu/qemu/commit/a859602c746baf4892cc8ca1ce003e92411d1716
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix FMUL8x16A{U,L}
These instructions have f32 inputs, which changes the decode
of the register numbers. While we're fixing things, use a
common helper for both insns, extracting the 16-bit scalar
in tcg beforehand.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20240502165528.244004-5-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: be8998e046c2a7e434494b75cf468ffd9d536025
https://github.com/qemu/qemu/commit/be8998e046c2a7e434494b75cf468ffd9d536025
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix FMULD8*X16
Not only do these instructions have f32 inputs, they also do not
perform rounding. Since these are relatively simple, implement
them properly inline.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240502165528.244004-6-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: d3ef26afde77fbdedd5b30282134ff99d0fe5cc5
https://github.com/qemu/qemu/commit/d3ef26afde77fbdedd5b30282134ff99d0fe5cc5
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix FPMERGE
This instruction has f32 inputs, which changes the decode
of the register numbers.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20240502165528.244004-7-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: d6f898cf85c92389182d22f0bcc3a11d7194fc94
https://github.com/qemu/qemu/commit/d6f898cf85c92389182d22f0bcc3a11d7194fc94
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-05 (Sun, 05 May 2024)
Changed paths:
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Split out do_ms16b
The unit operation for fmul8x16 and friends is described in the
manual as "MS16b". Split that out for clarity. Improve rounding
with an unconditional addition of 0.5 as a fixed-point integer.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20240502165528.244004-8-richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 1072f927f0966d37b37c52084b4eb957288b2704
https://github.com/qemu/qemu/commit/1072f927f0966d37b37c52084b4eb957288b2704
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M include/exec/cpu-all.h
Log Message:
-----------
exec/cpu: Indent TARGET_PAGE_foo definitions
The TARGET_PAGE_foo definitions are defined with multiple
level of #ifdef'ry. Indent it a bit for clarity.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240427155714.53669-6-phi...@linaro.org>
Commit: 86b7c5518232c8e5cda7951cbe62b0b23fc0b4e5
https://github.com/qemu/qemu/commit/86b7c5518232c8e5cda7951cbe62b0b23fc0b4e5
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/user-exec.c
M bsd-user/mmap.c
M include/exec/cpu-common.h
M linux-user/elfload.c
M linux-user/mmap.c
M target/cris/mmu.c
M target/microblaze/helper.c
Log Message:
-----------
exec/cpu: Rename PAGE_BITS macro to PAGE_RWX
This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC
for which PAGE_RWX is a better name and renaming it also shows it is
not related to TARGET_PAGE_BITS.
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240505121008.44a0d4e6...@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: a4f06b1a056b17336666c5fb218231259934dace
https://github.com/qemu/qemu/commit/a4f06b1a056b17336666c5fb218231259934dace
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M include/exec/cpu-all.h
Log Message:
-----------
exec/cpu: Remove obsolete PAGE_RESERVED definition
We stopped using the PAGE_RESERVED definition in commit
50d25c8aec ("accel/tcg: Drop PAGE_RESERVED for CONFIG_BSD").
This completes commit 2e9a5713f0 ("Remove PAGE_RESERVED").
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240427155714.53669-7-phi...@linaro.org>
Commit: 7dd1259b374ee32bf2a967697053e5401369c29d
https://github.com/qemu/qemu/commit/7dd1259b374ee32bf2a967697053e5401369c29d
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M include/exec/cpu-all.h
Log Message:
-----------
exec/cpu: Remove duplicated PAGE_PASSTHROUGH definition
Missed in commit 58771921af ("include/exec: Move PAGE_* macros
to common header"), PAGE_PASSTHROUGH ended being defined twice.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240427155714.53669-8-phi...@linaro.org>
Commit: 74781c0888e819552538593c0932d98ea16c766b
https://github.com/qemu/qemu/commit/74781c0888e819552538593c0932d98ea16c766b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M MAINTAINERS
M accel/tcg/cputlb.c
M accel/tcg/tb-maint.c
M accel/tcg/user-exec.c
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M bsd-user/qemu.h
M bsd-user/signal.c
M cpu-target.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/sam460ex.c
M hw/ppc/virtex_ml507.c
M include/exec/cpu-all.h
M include/exec/cpu-common.h
A include/exec/page-protection.h
M include/semihosting/uaccess.h
M linux-user/arm/cpu_loop.c
M linux-user/elfload.c
M linux-user/mmap.c
M linux-user/signal.c
M linux-user/syscall.c
M system/physmem.c
M target/alpha/helper.c
M target/arm/cpu.h
M target/arm/ptw.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/sve_helper.c
M target/avr/helper.c
M target/cris/mmu.c
M target/hppa/mem_helper.c
M target/hppa/translate.c
M target/i386/tcg/sysemu/excp_helper.c
M target/loongarch/tcg/tlb_helper.c
M target/m68k/helper.c
M target/microblaze/helper.c
M target/microblaze/mmu.c
M target/mips/sysemu/physaddr.c
M target/mips/tcg/sysemu/tlb_helper.c
M target/openrisc/mmu.c
M target/ppc/internal.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/riscv/cpu_helper.c
M target/riscv/pmp.c
M target/riscv/vector_helper.c
M target/rx/cpu.c
M target/s390x/mmu_helper.c
M target/s390x/tcg/mem_helper.c
M target/sh4/helper.c
M target/sparc/ldst_helper.c
M target/sparc/mmu_helper.c
M target/tricore/helper.c
M target/xtensa/mmu_helper.c
M target/xtensa/op_helper.c
Log Message:
-----------
exec/cpu: Extract page-protection definitions to page-protection.h
Extract page-protection definitions from "exec/cpu-all.h"
to "exec/page-protection.h".
The list of files requiring the new header was generated
using:
$ git grep -wE \
'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)'
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Nicholas Piggin <npig...@gmail.com>
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240427155714.53669-3-phi...@linaro.org>
Commit: 0650fc1ea33de8db48375664ae1dd1dc7ed72662
https://github.com/qemu/qemu/commit/0650fc1ea33de8db48375664ae1dd1dc7ed72662
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Use cpu_loop_exit_requested() in cpu_loop_exec_tb()
Do not open-code cpu_loop_exit_requested().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428214915.10339-9-phi...@linaro.org>
Commit: b254c342cfa4058257ded993fdb17870dcfa81b5
https://github.com/qemu/qemu/commit/b254c342cfa4058257ded993fdb17870dcfa81b5
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal-common.h
M accel/tcg/tcg-accel-ops.c
M include/exec/cpu-common.h
M include/exec/exec-all.h
M linux-user/mmap.c
M linux-user/syscall.c
M target/arm/cpu.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/cpu.c
M target/i386/helper.c
M target/loongarch/cpu.c
M target/microblaze/cpu.c
M target/mips/tcg/exception.c
M target/mips/tcg/sysemu/special_helper.c
M target/openrisc/cpu.c
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
Log Message:
-----------
accel/tcg: Access tcg_cflags with getter / setter
Access the CPUState::tcg_cflags via tcg_cflags_has() and
tcg_cflags_set() helpers.
Mechanical change using the following Coccinelle spatch script:
@@
expression cpu;
expression flags;
@@
- cpu->tcg_cflags & flags
+ tcg_cflags_has(cpu, flags)
@@
expression cpu;
expression flags;
@@
- (tcg_cflags_has(cpu, flags))
+ tcg_cflags_has(cpu, flags)
@@
expression cpu;
expression flags;
@@
- cpu->tcg_cflags |= flags;
+ tcg_cflags_set(cpu, flags);
Then manually moving the declarations, and adding both
tcg_cflags_has() and tcg_cflags_set() definitions.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240427155714.53669-15-phi...@linaro.org>
Commit: 40ab89f37498ae28b06e491d0d6fa3ecbf494363
https://github.com/qemu/qemu/commit/40ab89f37498ae28b06e491d0d6fa3ecbf494363
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Move user definition of cpu_interrupt() to user-exec.c
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428221450.26460-4-phi...@linaro.org>
Commit: b3e7bdeb78825b2aa050e2db7f122534a49d85e4
https://github.com/qemu/qemu/commit/b3e7bdeb78825b2aa050e2db7f122534a49d85e4
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M include/hw/core/cpu.h
Log Message:
-----------
accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentation
The @can_do_io field got moved from CPUState to
CPUNegativeOffsetState in commit 464dacf609 ("accel/tcg:
Move can_do_io to CPUNegativeOffsetState").
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428221450.26460-14-phi...@linaro.org>
Commit: 57d828429e5f1d849bf808387d947d7a62f0322e
https://github.com/qemu/qemu/commit/57d828429e5f1d849bf808387d947d7a62f0322e
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/core/cpu-common.c
Log Message:
-----------
accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG plugins
qemu_plugin_vcpu_exit_hook() is specific to TCG plugins,
so must be restricted to it in cpu_common_unrealizefn(),
similarly to how qemu_plugin_create_vcpu_state() is
restricted in the cpu_common_realizefn() counterpart.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240429213050.55177-2-phi...@linaro.org>
Commit: fc44d592db69547ca2fc1ec9ee41e6ea81734400
https://github.com/qemu/qemu/commit/fc44d592db69547ca2fc1ec9ee41e6ea81734400
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/internal-common.h
M include/hw/core/cpu.h
Log Message:
-----------
accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCG
So far cpu_plugin_mem_cbs_enabled() is only called from
TCG, so reduce it to accel/tcg/.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <5f59c754-44e5-4743-a2dd-87ef8e13e...@linaro.org>
Commit: 80f034c5b2040b3cfea978361dfd7d813e3c75d9
https://github.com/qemu/qemu/commit/80f034c5b2040b3cfea978361dfd7d813e3c75d9
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M accel/tcg/internal-common.h
M accel/tcg/plugin-gen.c
M include/hw/core/cpu.h
M include/qemu/plugin.h
M plugins/core.c
Log Message:
-----------
accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetState
@plugin_mem_cbs is accessed by tcg generated code, move it
to CPUNegativeOffsetState.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240429213050.55177-4-phi...@linaro.org>
Commit: 1d067e3953e76af28ba20c995b176fcbcb7a10aa
https://github.com/qemu/qemu/commit/1d067e3953e76af28ba20c995b176fcbcb7a10aa
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M scripts/qapi/introspect.py
M scripts/qapi/schema.py
M scripts/qapi/types.py
M scripts/qapi/visit.py
Log Message:
-----------
qapi: New QAPISchemaBranches, QAPISchemaAlternatives
QAPISchemaVariants represents either a union type's branches, or an
alternate type's alternatives. Much of its code is conditional on
which one it actually is.
Create QAPISchemaBranches for branches, and QAPISchemaAlternatives for
alternatives, both subtypes of QAPISchemaVariants.
Replace QAPISchemaVariants by one of them where possible. Keep it
only where we actually deal with either of them.
QAPISchemaVariants.__init__() takes @tag_name and @tag_member, where
exactly one must be None: @tag_name for alternatives, @tag_member for
branches. Let QAPISchemaBranches.__init__() take just @tag_name, and
QAPISchemaAlternatives.__init__() take just @tag_member.
A later patch will move the conditional code to the subtypes.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: d1da8af897340ed3773c09add93c3b9f494f2c2b
https://github.com/qemu/qemu/commit/d1da8af897340ed3773c09add93c3b9f494f2c2b
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M docs/sphinx/qapidoc.py
M scripts/qapi/introspect.py
M scripts/qapi/schema.py
M scripts/qapi/types.py
M scripts/qapi/visit.py
M tests/qapi-schema/test-qapi.py
Log Message:
-----------
qapi: Rename visitor parameter @variants to @branches
The previous commit narrowed the type of .visit_object_type()
parameter @variants from QAPISchemaVariants to QAPISchemaBranches.
Rename it to @branches.
Same for .visit_object_type_flat().
A few of these pass @branches to helper functions:
QAPISchemaGenRSTVisitor.visit_object_type() to ._nodes_for_members()
and ._nodes_for_variant_when(), and
QAPISchemaGenVisitVisitor.visit_object_type() to
gen_visit_object_members(). Rename the helpers' @variants parameters
to @branches as well.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: 41d0ad1d045a1af51200ff5f2a1309e4aada0a96
https://github.com/qemu/qemu/commit/41d0ad1d045a1af51200ff5f2a1309e4aada0a96
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M docs/sphinx/qapidoc.py
M scripts/qapi/introspect.py
M scripts/qapi/schema.py
M scripts/qapi/types.py
M scripts/qapi/visit.py
M tests/qapi-schema/test-qapi.py
Log Message:
-----------
qapi: Rename visitor parameter @variants to @alternatives
A previous commit narrowed the type of .visit_alternate_type()
parameter @variants from QAPISchemaVariants to QAPISchemaAlternatives.
Rename it to @alternatives.
One of them passes @alternatives to helper function
gen_visit_alternate(). Rename its @variants parameter to
@alternatives as well.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: 3ff2a5a35c387a4deb86101474c7e181b36e82f2
https://github.com/qemu/qemu/commit/3ff2a5a35c387a4deb86101474c7e181b36e82f2
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M scripts/qapi/commands.py
M scripts/qapi/events.py
M scripts/qapi/gen.py
M scripts/qapi/schema.py
M scripts/qapi/types.py
Log Message:
-----------
qapi: Rename QAPISchemaObjectType.variants to .branches
A previous commit narrowed the type of QAPISchemaObjectType.variants
from QAPISchemaVariants to QAPISchemaBranches. Rename it to
.branches.
Same for .__init__() parameter @variants.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: e0a28f39b4602de56d3c0f66a386ededd25ea109
https://github.com/qemu/qemu/commit/e0a28f39b4602de56d3c0f66a386ededd25ea109
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M scripts/qapi/schema.py
Log Message:
-----------
qapi: Rename QAPISchemaAlternateType.variants to .alternatives
A previous commit narrowed the type of
QAPISchemaAlternateType.variants from QAPISchemaVariants to
QAPISchemaAlternatives. Rename it to .alternatives.
Same for .__init__() parameter @variants.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: 8152bc7de6d4377d5104078115aa61986b436f44
https://github.com/qemu/qemu/commit/8152bc7de6d4377d5104078115aa61986b436f44
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M scripts/qapi/schema.py
Log Message:
-----------
qapi: Move conditional code from QAPISchemaVariants to its subtypes
QAPISchemaVariants.check()'s code is almost entirely conditional on
union vs. alternate type.
Move the conditional code to QAPISchemaBranches.check() and
QAPISchemaAlternatives.check(), where the conditions are always
satisfied.
Attribute QAPISchemaVariants.tag_name is now only used by
QAPISchemaBranches. Move it there.
Refactor the three types' .__init__() to make them a bit simpler.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: 285a8f209af7b4992aa91e8bea03a303fb6406ab
https://github.com/qemu/qemu/commit/285a8f209af7b4992aa91e8bea03a303fb6406ab
Author: Markus Armbruster <arm...@redhat.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M scripts/qapi/schema.py
Log Message:
-----------
qapi: Simplify QAPISchemaVariants @tag_member
For union types, the tag member is known only after .check().
We used to code this in a simple way: QAPISchemaVariants attribute
.tag_member was None for union types until .check().
Since this complicated typing, recent commit "qapi/schema: fix typing
for QAPISchemaVariants.tag_member" hid it behind a property.
The previous commit lets us treat .tag_member just like the other
attributes that become known only in .check(): declare, but don't
initialize it in .__init__().
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Commit: ef932e21bd83c1beab94b10989bf6e8424a886c2
https://github.com/qemu/qemu/commit/ef932e21bd83c1beab94b10989bf6e8424a886c2
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M bsd-user/qemu.h
M include/qemu/typedefs.h
M linux-user/qemu.h
Log Message:
-----------
user: Forward declare TaskState type definition
Forward declare TaskState in "qemu/typedefs.h" so we can
use it in generic headers like "hw/cpu/core.h".
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428221450.26460-9-phi...@linaro.org>
Commit: 8019601324159e76ccced4eb8d27093ec0011a54
https://github.com/qemu/qemu/commit/8019601324159e76ccced4eb8d27093ec0011a54
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
A accel/tcg/vcpu-state.h
M bsd-user/qemu.h
M linux-user/qemu.h
Log Message:
-----------
user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h'
While each user emulation implentation defines its own
TaskState structure, both use the same get_task_state()
declaration, in particular in common code (such gdbstub).
Declare the method once in "accel/tcg/vcpu-state.h".
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428221450.26460-10-phi...@linaro.org>
Commit: 59272469bd1365564fe0bb2c10d8c1d25acd51a6
https://github.com/qemu/qemu/commit/59272469bd1365564fe0bb2c10d8c1d25acd51a6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M gdbstub/gdbstub.c
M gdbstub/user-target.c
M linux-user/syscall.c
Log Message:
-----------
user: Use get_task_state() helper
Get the TaskState pointer calling get_task_state().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20240428221450.26460-11-phi...@linaro.org>
Commit: a99dd3375c1280b350b36527e0e8756ce44c4e8a
https://github.com/qemu/qemu/commit/a99dd3375c1280b350b36527e0e8756ce44c4e8a
Author: Juergen Gross <jgr...@suse.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M system/physmem.c
Log Message:
-----------
system: let qemu_map_ram_ptr() use qemu_ram_ptr_length()
qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so
modify qemu_ram_ptr_length() a little bit and use it for
qemu_map_ram_ptr(), too.
Signed-off-by: Juergen Gross <jgr...@suse.com>
Signed-off-by: Vikram Garhwal <vikram.garh...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-Id: <20240227223501.28475-4-vikram.garh...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Acked-by: David Hildenbrand <da...@redhat.com>
Reviewed-by: Peter Xu <pet...@redhat.com>
Message-ID: <20240430164939.925307-2-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 337265dbf2c35bdfc26f19ed05a71d225318660b
https://github.com/qemu/qemu/commit/337265dbf2c35bdfc26f19ed05a71d225318660b
Author: Juergen Gross <jgr...@suse.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entry
Today xen_ram_addr_from_mapcache() will either abort() or return 0 in
case it can't find a matching entry for a pointer value. Both cases
are bad, so change that to return an invalid address instead.
Signed-off-by: Juergen Gross <jgr...@suse.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Message-Id: <20231005181629.4046-5-vikram.garh...@amd.com>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Message-ID: <20240430164939.925307-3-edgar.igles...@gmail.com>
[PMD: Keep xen_ram_addr_from_mapcache_not_found trace event]
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: efb0c6caefca19a4c9150306013927c0a2ca828e
https://github.com/qemu/qemu/commit/efb0c6caefca19a4c9150306013927c0a2ca828e
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Refactor lock functions for multi-instance
Make the lock functions take MapCache * as argument. This is
in preparation for supporting multiple caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Message-ID: <20240430164939.925307-4-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: eda3a8cd2e1ba6328ef8a72c498f87e4e11d059e
https://github.com/qemu/qemu/commit/eda3a8cd2e1ba6328ef8a72c498f87e4e11d059e
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Refactor xen_map_cache for multi-instance
Make xen_map_cache take a MapCache as argument. This is in
prepaparation to support multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Message-ID: <20240430164939.925307-5-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 9b1f33fa63e1cf696273a77c98bb8a1efcdc048c
https://github.com/qemu/qemu/commit/9b1f33fa63e1cf696273a77c98bb8a1efcdc048c
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Refactor xen_remap_bucket for multi-instance
Add MapCache argument to xen_remap_bucket in preparation
to support multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240430164939.925307-6-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 9b005553548f2872ec913d3cf66db22d5b7c205a
https://github.com/qemu/qemu/commit/9b005553548f2872ec913d3cf66db22d5b7c205a
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Break out xen_ram_addr_from_mapcache_single
Break out xen_ram_addr_from_mapcache_single(), a multi-cache
aware version of xen_ram_addr_from_mapcache.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240430164939.925307-7-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 8be27f50ac7a788f1e7f7e0b4d519d3916a74ec8
https://github.com/qemu/qemu/commit/8be27f50ac7a788f1e7f7e0b4d519d3916a74ec8
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Refactor xen_replace_cache_entry_unlocked
Add MapCache argument to xen_replace_cache_entry_unlocked in
preparation for supporting multiple map caches.
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240430164939.925307-8-edgar.igles...@gmail.com>
[PMD: Remove last global mapcache pointer, reported by sstabellini]
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 87b5a05a853c70756fc94f53e68587c00370aa0d
https://github.com/qemu/qemu/commit/87b5a05a853c70756fc94f53e68587c00370aa0d
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlocked
Add MapCache argument to xen_invalidate_map_cache_entry_unlocked.
This is in preparation for supporting multiple map caches.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240430164939.925307-9-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 946b4c9bc319fd8a36dad8fad4f301856315ba8f
https://github.com/qemu/qemu/commit/946b4c9bc319fd8a36dad8fad4f301856315ba8f
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Break out xen_invalidate_map_cache_single()
Break out xen_invalidate_map_cache_single().
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240430164939.925307-10-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 886e5ade919647e0dc7276a40b2d6cd6e2f9c85c
https://github.com/qemu/qemu/commit/886e5ade919647e0dc7276a40b2d6cd6e2f9c85c
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
Log Message:
-----------
xen: mapcache: Break out xen_map_cache_init_single()
Break out xen_map_cache_init_single() in preparation for
adding multiple map caches.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Message-ID: <20240430164939.925307-11-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 5a5585f45dcf32fde57bd1b4015fd2f00c52867c
https://github.com/qemu/qemu/commit/5a5585f45dcf32fde57bd1b4015fd2f00c52867c
Author: Edgar E. Iglesias <edgar.igles...@amd.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M hw/xen/xen-mapcache.c
M include/sysemu/xen-mapcache.h
M system/physmem.c
Log Message:
-----------
system: Pass RAM MemoryRegion and is_write in xen_map_cache()
Propagate MR and is_write to xen_map_cache().
This is in preparation for adding support for grant mappings.
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Reviewed-by: David Hildenbrand <da...@redhat.com>
Message-ID: <20240430164939.925307-14-edgar.igles...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 45c577f380a89b2e4e09f369e5648ff5b451de96
https://github.com/qemu/qemu/commit/45c577f380a89b2e4e09f369e5648ff5b451de96
Author: Aleksandar Rikalo <aleksandar.rik...@syrmia.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update Aleksandar Rikalo email
Syrmia LLC has been acquired recently and the syrmia.com domain will
disappear soon, so updating my email in the MAINTAINERS file.
Signed-off-by: Aleksandar Rikalo <aleksandar.rik...@syrmia.com>
Message-ID: <20240209062147.62453-1-aleksandar.rik...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 8372c3a0cbc5d41458ab3582164cfbcac9b434d4
https://github.com/qemu/qemu/commit/8372c3a0cbc5d41458ab3582164cfbcac9b434d4
Author: Bin Meng <bin.meng...@windriver.com>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update my email address
The old Wind River email address (bin.m...@windriver.com) is no longer
available due to an internal infrastructure change within the company.
While a new email address (bin.meng...@windriver.com) has been assigned
to me, I am unable to find a way to send this patch directly from the
new address. Presumably, the basic authentication with client submission
(SMTP AUTH) [1] has been disabled by the company's IT.
Switch to use my personal email address instead.
Signed-off-by: Bin Meng <bin.meng...@windriver.com>
Signed-off-by: Bin Meng <bmeng...@gmail.com>
[1]
https://learn.microsoft.com/en-us/exchange/mail-flow-best-practices/how-to-set-up-a-multifunction-device-or-application-to-send-email-using-microsoft-365-or-office-365
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20240505072312.2776074-1-bmeng...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: 604dc98970d1c2944b9c529f4474cf16b324067c
https://github.com/qemu/qemu/commit/604dc98970d1c2944b9c529f4474cf16b324067c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M docs/sphinx/qapidoc.py
M scripts/qapi/commands.py
M scripts/qapi/events.py
M scripts/qapi/gen.py
M scripts/qapi/introspect.py
M scripts/qapi/schema.py
M scripts/qapi/types.py
M scripts/qapi/visit.py
M tests/qapi-schema/test-qapi.py
Log Message:
-----------
Merge tag 'pull-qapi-2024-05-06' of https://repo.or.cz/qemu/armbru into
staging
QAPI patches patches for 2024-05-06
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# gpg: Signature made Mon 06 May 2024 04:01:20 AM PDT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "arm...@redhat.com"
# gpg: Good signature from "Markus Armbruster <arm...@redhat.com>" [full]
# gpg: aka "Markus Armbruster <arm...@pond.sub.org>" [full]
* tag 'pull-qapi-2024-05-06' of https://repo.or.cz/qemu/armbru:
qapi: Simplify QAPISchemaVariants @tag_member
qapi: Move conditional code from QAPISchemaVariants to its subtypes
qapi: Rename QAPISchemaAlternateType.variants to .alternatives
qapi: Rename QAPISchemaObjectType.variants to .branches
qapi: Rename visitor parameter @variants to @alternatives
qapi: Rename visitor parameter @variants to @branches
qapi: New QAPISchemaBranches, QAPISchemaAlternatives
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 873f9ca3857cfeeef45441b116c91156736d529c
https://github.com/qemu/qemu/commit/873f9ca3857cfeeef45441b116c91156736d529c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M MAINTAINERS
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/internal-common.h
M accel/tcg/plugin-gen.c
M accel/tcg/tb-maint.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
A accel/tcg/vcpu-state.h
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M bsd-user/qemu.h
M bsd-user/signal.c
M cpu-target.c
M gdbstub/gdbstub.c
M gdbstub/user-target.c
M hw/core/cpu-common.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/sam460ex.c
M hw/ppc/virtex_ml507.c
M hw/xen/xen-mapcache.c
M include/exec/cpu-all.h
M include/exec/cpu-common.h
M include/exec/exec-all.h
A include/exec/page-protection.h
M include/hw/core/cpu.h
M include/qemu/plugin.h
M include/qemu/typedefs.h
M include/semihosting/uaccess.h
M include/sysemu/xen-mapcache.h
M linux-user/arm/cpu_loop.c
M linux-user/elfload.c
M linux-user/mmap.c
M linux-user/qemu.h
M linux-user/signal.c
M linux-user/syscall.c
M plugins/core.c
M system/physmem.c
M target/alpha/helper.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/ptw.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/sve_helper.c
M target/avr/cpu.c
M target/avr/helper.c
M target/cris/mmu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/hppa/mem_helper.c
M target/hppa/translate.c
M target/i386/cpu.c
M target/i386/helper.c
M target/i386/tcg/sysemu/excp_helper.c
M target/loongarch/cpu.c
M target/loongarch/tcg/tlb_helper.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/microblaze/helper.c
M target/microblaze/mmu.c
M target/mips/sysemu/physaddr.c
M target/mips/tcg/exception.c
M target/mips/tcg/sysemu/special_helper.c
M target/mips/tcg/sysemu/tlb_helper.c
M target/openrisc/cpu.c
M target/openrisc/mmu.c
M target/ppc/internal.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/riscv/cpu_helper.c
M target/riscv/pmp.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/vector_helper.c
M target/rx/cpu.c
M target/s390x/mmu_helper.c
M target/s390x/tcg/mem_helper.c
M target/sh4/cpu.c
M target/sh4/helper.c
M target/sparc/cpu.c
M target/sparc/ldst_helper.c
M target/sparc/mmu_helper.c
M target/tricore/cpu.c
M target/tricore/helper.c
M target/xtensa/mmu_helper.c
M target/xtensa/op_helper.c
Log Message:
-----------
Merge tag 'accel-20240506' of https://github.com/philmd/qemu into staging
Accelerator patches
- Extract page-protection definitions to page-protection.h
- Rework in accel/tcg in preparation of extracting TCG fields from CPUState
- More uses of get_task_state() in user emulation
- Xen refactors in preparation for adding multiple map caches (Juergen & Edgar)
- MAINTAINERS updates (Aleksandar and Bin)
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# gpg: Signature made Mon 06 May 2024 05:42:08 AM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4...@amsat.org>"
[full]
* tag 'accel-20240506' of https://github.com/philmd/qemu: (28 commits)
MAINTAINERS: Update my email address
MAINTAINERS: Update Aleksandar Rikalo email
system: Pass RAM MemoryRegion and is_write in xen_map_cache()
xen: mapcache: Break out xen_map_cache_init_single()
xen: mapcache: Break out xen_invalidate_map_cache_single()
xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlocked
xen: mapcache: Refactor xen_replace_cache_entry_unlocked
xen: mapcache: Break out xen_ram_addr_from_mapcache_single
xen: mapcache: Refactor xen_remap_bucket for multi-instance
xen: mapcache: Refactor xen_map_cache for multi-instance
xen: mapcache: Refactor lock functions for multi-instance
xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entry
system: let qemu_map_ram_ptr() use qemu_ram_ptr_length()
user: Use get_task_state() helper
user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h'
user: Forward declare TaskState type definition
accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetState
accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCG
accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG plugins
accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentation
...
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e116b92d01c2cd75957a9f8ad1d4932292867b81
https://github.com/qemu/qemu/commit/e116b92d01c2cd75957a9f8ad1d4932292867b81
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-06 (Mon, 06 May 2024)
Changed paths:
M docs/about/deprecated.rst
M docs/system/target-sparc.rst
M hw/sparc64/sun4u.c
M linux-user/elfload.c
M qom/object.c
M target/sparc/cpu.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into
staging
qemu-sparc queue
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# gpg: Signature made Mon 06 May 2024 04:40:07 AM PDT
# gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "mark.cave-ayl...@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>"
[full]
* tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu:
target/sparc: Split out do_ms16b
target/sparc: Fix FPMERGE
target/sparc: Fix FMULD8*X16
target/sparc: Fix FMUL8x16A{U,L}
target/sparc: Fix FMUL8x16
target/sparc: Fix FEXPAND
linux-user/sparc: Add more hwcap bits for sparc64
hw/sparc64: set iommu_platform=on for virtio devices attached to the sun4u
machine
docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+"
docs/system/target-sparc: Improve the Sparc documentation
target/sparc/cpu: Avoid spaces by default in the CPU names
target/sparc/cpu: Rename the CPU models with a "+" in their names
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d4c453f64824...e116b92d01c2
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