Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: b776569a53f70ab4661ed627756385b05dcaf75e
https://github.com/qemu/qemu/commit/b776569a53f70ab4661ed627756385b05dcaf75e
Author: Babu Moger <babu.mo...@amd.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M hw/i386/pc.c
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Fix CPUID encoding of Fn8000001E_ECX
Observed the following failure while booting the SEV-SNP guest and the
guest fails to boot with the smp parameters:
"-smp 192,sockets=1,dies=12,cores=8,threads=2".
qemu-system-x86_64: sev_snp_launch_update: SNP_LAUNCH_UPDATE ret=-5 fw_error=22
'Invalid parameter'
qemu-system-x86_64: SEV-SNP: CPUID validation failed for function 0x8000001e,
index: 0x0.
provided: eax:0x00000000, ebx: 0x00000100, ecx: 0x00000b00, edx: 0x00000000
expected: eax:0x00000000, ebx: 0x00000100, ecx: 0x00000300, edx: 0x00000000
qemu-system-x86_64: SEV-SNP: failed update CPUID page
Reason for the failure is due to overflowing of bits used for "Node per
processor" in CPUID Fn8000001E_ECX. This field's width is 3 bits wide and
can hold maximum value 0x7. With dies=12 (0xB), it overflows and spills
over into the reserved bits. In the case of SEV-SNP, this causes CPUID
enforcement failure and guest fails to boot.
The PPR documentation for CPUID_Fn8000001E_ECX [Node Identifiers]
=================================================================
Bits Description
31:11 Reserved.
10:8 NodesPerProcessor: Node per processor. Read-only.
ValidValues:
Value Description
0h 1 node per processor.
7h-1h Reserved.
7:0 NodeId: Node ID. Read-only. Reset: Fixed,XXh.
=================================================================
As in the spec, the valid value for "node per processor" is 0 and rest
are reserved.
Looking back at the history of decoding of CPUID_Fn8000001E_ECX, noticed
that there were cases where "node per processor" can be more than 1. It
is valid only for pre-F17h (pre-EPYC) architectures. For EPYC or later
CPUs, the linux kernel does not use this information to build the L3
topology.
Also noted that the CPUID Function 0x8000001E_ECX is available only when
TOPOEXT feature is enabled. This feature is enabled only for EPYC(F17h)
or later processors. So, previous generation of processors do not not
enumerate 0x8000001E_ECX leaf.
There could be some corner cases where the older guests could enable the
TOPOEXT feature by running with -cpu host, in which case legacy guests
might notice the topology change. To address those cases introduced a
new CPU property "legacy-multi-node". It will be true for older machine
types to maintain compatibility. By default, it will be false, so new
decoding will be used going forward.
The documentation is taken from Preliminary Processor Programming
Reference (PPR) for AMD Family 19h Model 11h, Revision B1 Processors 55901
Rev 0.25 - Oct 6, 2022.
Cc: qemu-sta...@nongnu.org
Fixes: 31ada106d891 ("Simplify CPUID_8000_001E for AMD")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Message-ID:
<0ee4b0a8293188a53970a2b0e4f4ef713425055e.1714757834.git.babu.mo...@amd.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 15957eb9efe2da67c796612cead95cba28ba9bda
https://github.com/qemu/qemu/commit/15957eb9efe2da67c796612cead95cba28ba9bda
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: use TSTEQ/TSTNE to test low bits
When testing the sign bit or equality to zero of a partial register, it
is useful to use a single TSTEQ or TSTNE operation. It can also be used
to test the parity flag, using bit 0 of the population count.
Do not do this for target_ulong-sized values however; the optimizer would
produce a comparison against zero anyway, and it avoids shifts by 64
which are undefined behavior.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 9309b53e835f5d1d7795d81399cda7ecf99321e1
https://github.com/qemu/qemu/commit/9309b53e835f5d1d7795d81399cda7ecf99321e1
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: use TSTEQ/TSTNE to check flags
The new conditions obviously come in handy when testing individual bits
of EFLAGS, and they make it possible to remove the .mask field of
CCPrepare.
Lowering to shift+and is done by the optimizer if necessary.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: e995f3f9442ce0cb869737ce100c3ebbba651809
https://github.com/qemu/qemu/commit/e995f3f9442ce0cb869737ce100c3ebbba651809
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: remove mask from CCPrepare
With the introduction of TSTEQ and TSTNE the .mask field is always -1,
so remove all the now-unnecessary code.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 64ddadc6bb80376da2a818b38ae6a51fe1b7f5f2
https://github.com/qemu/qemu/commit/64ddadc6bb80376da2a818b38ae6a51fe1b7f5f2
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: cc_op is not dynamic in gen_jcc1
Resetting cc_op to CC_OP_DYNAMIC should be done at control flow junctions,
which is not the case here. This translation block is ending and the
only effect of calling set_cc_op() would be a discard of s->cc_srcT.
This discard is useless (it's a temporary, not a global) and in fact
prevents gen_prepare_cc from returning s->cc_srcT.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: bbba9594e84f60707558cce9cd3e4d70b9bd0fec
https://github.com/qemu/qemu/commit/bbba9594e84f60707558cce9cd3e4d70b9bd0fec
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: cleanup cc_op changes for REP/REPZ/REPNZ
gen_update_cc_op must be called before control flow splits. Do it
where the jump on ECX!=0 is translated.
On the other hand, remove the call before gen_jcc1, which takes care of
it already, and explain why REPZ/REPNZ need not use CC_OP_DYNAMIC---the
translation block ends before any control-flow-dependent cc_op could
be observed.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: dd17322be7c6aa07ba792d661f1920c717ad5c94
https://github.com/qemu/qemu/commit/dd17322be7c6aa07ba792d661f1920c717ad5c94
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize}
gen_update_cc_op must be called before control flow splits. Doing it
in gen_jmp_rel{,_csize} may hide bugs, instead assert that cc_op is
clean---even if that means a few more calls to gen_update_cc_op().
With this new invariant, setting cc_op to CC_OP_DYNAMIC is unnecessary
since the caller should have done it.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: bccb0c138e5138c86169216bce280b1ebde44e1b
https://github.com/qemu/qemu/commit/bccb0c138e5138c86169216bce280b1ebde44e1b
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: extend cc_* when using them to compute flags
Instead of using s->tmp0 or s->tmp4 as the result, just extend the cc_*
registers in place. It is harmless and, if multiple setcc instructions
are used, the optimizer will be able to remove the redundant ones.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 89e4e65ac0efd8d55d47fb7150d801ca4586872e
https://github.com/qemu/qemu/commit/89e4e65ac0efd8d55d47fb7150d801ca4586872e
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare
Instead of using s->T0 or s->T1, create a scratch register
when computing the C, NC, L or LE conditions.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ccfabc00e01d41a296502a437ac8aa50139720fc
https://github.com/qemu/qemu/commit/ccfabc00e01d41a296502a437ac8aa50139720fc
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: clarify the "reg" argument of functions returning CCPrepare
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 8b5de7ea562ff142b324d996bad4118248b7274f
https://github.com/qemu/qemu/commit/8b5de7ea562ff142b324d996bad4118248b7274f
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: cleanup *gen_eob*
Create a new wrapper for syscall/sysret, and do not go through multiple
layers of wrappers.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 445457693cbb5bf50765d5d29ca35dd357f8dbaa
https://github.com/qemu/qemu/commit/445457693cbb5bf50765d5d29ca35dd357f8dbaa
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reintroduce debugging mechanism
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: cc1d28bdbe0f0abe75ff94518458e090137c5ea6
https://github.com/qemu/qemu/commit/cc1d28bdbe0f0abe75ff94518458e090137c5ea6
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move 00-5F opcodes to new decoder
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 442e38c4fb9b89fb2b3c9ac3e661c93aa1dc40f9
https://github.com/qemu/qemu/commit/442e38c4fb9b89fb2b3c9ac3e661c93aa1dc40f9
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: extract gen_far_call/jmp, reordering temporaries
Extract the code into new functions, and swap T0/T1 so that T0 corresponds
to the first immediate in the instruction stream.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 2666fbd271fdaae8b2956baf0a096e77c9b3c793
https://github.com/qemu/qemu/commit/2666fbd271fdaae8b2956baf0a096e77c9b3c793
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: allow instructions with more than one immediate
While keeping decode->immediate for convenience and for 4-operand instructions,
store the immediate in X86DecodedOp as well. This enables instructions
with more than one immediate such as ENTER. It can also be used for far
calls and jumps.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 5e9e21bcc4d22dbd4473cab494a1beefbd3786a9
https://github.com/qemu/qemu/commit/5e9e21bcc4d22dbd4473cab494a1beefbd3786a9
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move 60-BF opcodes to new decoder
Compared to the old decoder, the main differences in translation
are for the little-used ARPL instruction. IMUL is adjusted a bit
to share more code to produce flags, but is otherwise very similar.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: b603136402d2ae217b5051cd041a8591f09b04ba
https://github.com/qemu/qemu/commit/b603136402d2ae217b5051cd041a8591f09b04ba
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: generalize gen_movl_seg_T0
In the new decoder it is sometimes easier to put the segment
in T1 instead of T0, usually because another operand was loaded
by common code in T0. Genrealize gen_movl_seg_T0 to allow
using any source.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d7c41a60d0c5228d5adfc73c83facb1307a1d45e
https://github.com/qemu/qemu/commit/d7c41a60d0c5228d5adfc73c83facb1307a1d45e
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move C0-FF opcodes to new decoder (except for x87)
The shift instructions are rewritten instead of reusing code from the old
decoder. Rotates use CC_OP_ADCOX more extensively and generally rely
more on the optimizer, so that the code generators are shared between
the immediate-count and variable-count cases.
In particular, this makes gen_RCL and gen_RCR pretty efficient for the
count == 1 case, which becomes (apart from a few extra movs) something like:
(compute_cc_all if needed)
// save old value for OF calculation
mov cc_src2, T0
// the bulk of RCL is just this!
deposit T0, cc_src, T0, 1, TARGET_LONG_BITS - 1
// compute carry
shr cc_dst, cc_src2, length - 1
and cc_dst, cc_dst, 1
// compute overflow
xor cc_src2, cc_src2, T0
extract cc_src2, cc_src2, length - 1, 1
32-bit MUL and IMUL are also slightly more efficient on 64-bit hosts.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 40c4b92f1c8df3b501484511f319d7220fd72eca
https://github.com/qemu/qemu/commit/40c4b92f1c8df3b501484511f319d7220fd72eca
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: merge and enlarge a few ranges for call to disas_insn_new
Since new opcodes are not going to be added in translate.c, round the
case labels that call to disas_insn_new(), including whole sets of
eight opcodes when possible.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 2b8046f3618756dee9c8169bc389b890c43f7190
https://github.com/qemu/qemu/commit/2b8046f3618756dee9c8169bc389b890c43f7190
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move remaining conditional operations to new decoder
Move long-displacement Jcc, SETcc and CMOVcc to the new decoder.
While filling in the tables makes the code seem longer, the new
emitters are all just one line of code.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 37861fa519a97324dbca67ee4c5b23bec21c24db
https://github.com/qemu/qemu/commit/37861fa519a97324dbca67ee4c5b23bec21c24db
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move BSWAP to new decoder
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 3519b813e1f1657d06b5af73bcbe50f6ba176a29
https://github.com/qemu/qemu/commit/3519b813e1f1657d06b5af73bcbe50f6ba176a29
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: port extensions of one-byte opcodes to new decoder
A few two-byte opcodes are simple extensions of existing one-byte opcodes;
they are easy to decode and need no change to emit.c.inc. Port them to
the new decoder.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: aef4f4affde2c8d644e8a509171d5995a3983f56
https://github.com/qemu/qemu/commit/aef4f4affde2c8d644e8a509171d5995a3983f56
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/helper.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/int_helper.c
R target/i386/tcg/shift_helper_template.h.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: remove now-converted opcodes from old decoder
Send all converted opcodes to disas_insn_new() directly from the big
decoding switch statement; once more, the debugging/bisecting logic
disappears.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 7795b455ddc491946c90953358b36915d42d386a
https://github.com/qemu/qemu/commit/7795b455ddc491946c90953358b36915d42d386a
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: decode x87 instructions in a separate function
These are unlikely to be converted to the table-based decoding
soon (perhaps there could be generic ESC decoding in decode-new.c.inc
for the Mod/RM byte, but not operand decoding), so keep them separate
from the remaining legacy-decoded instructions.
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ef309ec2a6fab1265950c831b16c3e6a9e72a9c1
https://github.com/qemu/qemu/commit/ef309ec2a6fab1265950c831b16c3e6a9e72a9c1
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: split legacy decoder into a separate function
Split the bits that have some duplication with disas_insn_new, from
those that should be the main topic of the conversion. This is the
first step towards removing duplicate decoding of prefixes between
disas_insn and disas_insn_new.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d4e6d40c36071c287199c072cd5d296091ee5968
https://github.com/qemu/qemu/commit/d4e6d40c36071c287199c072cd5d296091ee5968
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: remove duplicate prefix decoding
Now that a bulk of opcodes go through the new decoder, it is sensible
to do some cleanup. Go immediately through disas_insn_new and only jump
back after parsing the prefixes.
disas_insn() now only contains the three sigsetjmp cases, and they
are more easily managed if they are inlined into i386_tr_translate_insn.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4e66a08546a2588a4667766a1edab9caccf24ce3
https://github.com/qemu/qemu/commit/4e66a08546a2588a4667766a1edab9caccf24ce3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-07 (Tue, 07 May 2024)
Changed paths:
M hw/i386/pc.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/helper.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/int_helper.c
R target/i386/tcg/shift_helper_template.h.inc
M target/i386/tcg/translate.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386/tcg: conversion of one byte opcodes to table-based decoder
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# gpg: Signature made Mon 06 May 2024 11:53:40 PM PDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonz...@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonz...@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonz...@redhat.com>" [full]
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (26 commits)
target/i386: remove duplicate prefix decoding
target/i386: split legacy decoder into a separate function
target/i386: decode x87 instructions in a separate function
target/i386: remove now-converted opcodes from old decoder
target/i386: port extensions of one-byte opcodes to new decoder
target/i386: move BSWAP to new decoder
target/i386: move remaining conditional operations to new decoder
target/i386: merge and enlarge a few ranges for call to disas_insn_new
target/i386: move C0-FF opcodes to new decoder (except for x87)
target/i386: generalize gen_movl_seg_T0
target/i386: move 60-BF opcodes to new decoder
target/i386: allow instructions with more than one immediate
target/i386: extract gen_far_call/jmp, reordering temporaries
target/i386: move 00-5F opcodes to new decoder
target/i386: reintroduce debugging mechanism
target/i386: cleanup *gen_eob*
target/i386: clarify the "reg" argument of functions returning CCPrepare
target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare
target/i386: extend cc_* when using them to compute flags
target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize}
...
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/571882c668a0...4e66a08546a2
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