Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c700b5e162208a0fa4211fc6d9dab271b1342640
https://github.com/qemu/qemu/commit/c700b5e162208a0fa4211fc6d9dab271b1342640
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M hw/ppc/pegasos2.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/kvm.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
Log Message:
-----------
spapr: avoid overhead of finding vhyp class in critical operations
PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
interrupts and TLB misses and is quite costly. Running the
kvm-unit-tests sieve program with radix MMU enabled thrashes the TCG
TLB and spends a lot of time in TLB and page table walking code. The
test takes 67 seconds to complete with a lot of time being spent in
code related to finding the vhyp class:
12.01% [.] g_str_hash
8.94% [.] g_hash_table_lookup
8.06% [.] object_class_dynamic_cast
6.21% [.] address_space_ldq
4.94% [.] __strcmp_avx2
4.28% [.] tlb_set_page_full
4.08% [.] address_space_translate_internal
3.17% [.] object_class_dynamic_cast_assert
2.84% [.] ppc_radix64_xlate
Keep a pointer to the class and avoid this lookup. This reduces the
execution time to 40 seconds.
Reviewed-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 95912ce1ebe4303d17118219691573ae6227b0e2
https://github.com/qemu/qemu/commit/95912ce1ebe4303d17118219691573ae6227b0e2
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: Add ibm,pi-features
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Reviewed-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 82676f1fc4b1511a5fe32256aaec885d200ffbf6
https://github.com/qemu/qemu/commit/82676f1fc4b1511a5fe32256aaec885d200ffbf6
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper_regs.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
M target/ppc/translate/storage-ctrl-impl.c.inc
Log Message:
-----------
target/ppc: Fix broadcast tlbie synchronisation
With mttcg, broadcast tlbie instructions do not wait until other vCPUs
have been kicked out of TCG execution before they complete (including
necessary subsequent tlbsync, etc., instructions). This is contrary to
the ISA, and it permits other vCPUs to use translations after the TLB
flush. For example:
CPU0
// *memP is initially 0, memV maps to memP with *pte
*pte = 0;
ptesync ; tlbie ; eieio ; tlbsync ; ptesync
*memP = 1;
CPU1
assert(*memV == 0);
It is possible for the assertion to fail because CPU1 translates memV
using the TLB after CPU0 has stored 1 to the underlying memory. This
race was observed with a careful test case where CPU1 checks run in a
very large expensive TB so it can run for the entire CPU0 period between
clearing the pte and storing the memory, but host vCPU thread preemption
could cause the race to hit anywhere.
As explained in commit 4ddc104689b ("target/ppc: Fix tlbie"), it is not
enough to just use tlb_flush_all_cpus_synced(), because that does not
execute until the calling CPU has finished its TB. It is also required
that the TB is ended at the point where the TLB flush must subsequently
take effect.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 99cd12ced16d15a1ffde055f842497747f070f91
https://github.com/qemu/qemu/commit/99cd12ced16d15a1ffde055f842497747f070f91
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M accel/tcg/cputlb.c
M docs/devel/multi-thread-tcg.rst
M include/exec/exec-all.h
Log Message:
-----------
tcg/cputlb: Remove non-synced variants of global TLB flushes
These are no longer used.
tlb_flush_all_cpus: removed by previous commit.
tlb_flush_page_all_cpus: removed by previous commit.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used.
tlb_flush_page_by_mmuidx_all_cpus: never used.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used, thus:
tlb_flush_range_by_mmuidx_all_cpus: never used.
tlb_flush_by_mmuidx_all_cpus: never used.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 30933c4fb4f3df95ae44c4c3c86a5df049852c01
https://github.com/qemu/qemu/commit/30933c4fb4f3df95ae44c4c3c86a5df049852c01
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
tcg/cputlb: remove other-cpu capability from TLB flushing
Some TLB flush operations can flush other CPUs. The problem with this
is they used non-synced variants of flushes (i.e., that return
before the destination has completed the flush). Since all TLB flush
users need the _synced variants, and that last user (ppc) of the
non-synced flush was buggy, this is a footgun waiting to go off. There
do not seem to be any callers that flush other CPUs, so remove the
capability.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 13f50867837874892f33c32a4452843d9ce7144c
https://github.com/qemu/qemu/commit/13f50867837874892f33c32a4452843d9ce7144c
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/misc-impl.c.inc
Log Message:
-----------
target/ppc: Move sync instructions to decodetree
This tries to faithfully reproduce the odd BookE logic. Note the
e206 check in gen_msync_4xx() is always false, so not carried over.
It does change the handling of non-zero reserved bits outside the
defined fields from being illegal to being ignored, which the
architecture specifies ot help with backward compatibility of new
fields. The existing behaviour causes illegal instruction exceptions
when using new POWER10 sync variants that add new fields, after this
the instructions are accepted and are implemented as supersets of
the new behaviour, as intended.
Reviewed-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: ab4f174baee4b28b454fc94a7de2978c13a423ac
https://github.com/qemu/qemu/commit/ab4f174baee4b28b454fc94a7de2978c13a423ac
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/translate/misc-impl.c.inc
Log Message:
-----------
target/ppc: Fix embedded memory barriers
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Reviewed-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752
https://github.com/qemu/qemu/commit/b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/misc-impl.c.inc
Log Message:
-----------
target/ppc: Add ISA v3.1 variants of sync instruction
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Reviewed-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 5747926fec6c65b60f9f7aca6d4df525c79eae8e
https://github.com/qemu/qemu/commit/5747926fec6c65b60f9f7aca6d4df525c79eae8e
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Merge various fpu helpers
This patch merges the definitions of the following set of fpu helper methods,
which are similar, using macros :
1. f{add, sub, mul, div}(s)
2. fre(s)
3. frsqrte(s)
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 177fcc06dc579749ec4515174b62ba4cdb775474
https://github.com/qemu/qemu/commit/177fcc06dc579749ec4515174b62ba4cdb775474
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Move floating-point arithmetic instructions to decodetree.
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: a1faff873ab1b808126a110aa6b3bc6050baa0f1
https://github.com/qemu/qemu/commit/a1faff873ab1b808126a110aa6b3bc6050baa0f1
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Also cleaned up code for mullw[o][.] as per review comments while
keeping the logic of the tcg ops generated semantically same.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab
https://github.com/qemu/qemu/commit/86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Make divw[u] handler method decodetree compatible.
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 2871921d857d3137e160dcb57ae0b48ddc98822f
https://github.com/qemu/qemu/commit/2871921d857d3137e160dcb57ae0b48ddc98822f
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move divw[u, e, eu] instructions to decodetree.
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: a81b5c186730fe5a92b645c84e538444a64b93f5
https://github.com/qemu/qemu/commit/a81b5c186730fe5a92b645c84e538444a64b93f5
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move neg, darn, mod{sw, uw} to decodetree.
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 703e88f72325c46daa1a47c28469d814dd850d4c
https://github.com/qemu/qemu/commit/703e88f72325c46daa1a47c28469d814dd850d4c
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree.
Moving the following instructions to decodetree :
mul{ld, ldo, hd, hdu}[.] : XO-form
madd{hd, hdu, ld} : VA-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op'
flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: f424bc10ebf2a935a2c20400996d665434ec9e17
https://github.com/qemu/qemu/commit/f424bc10ebf2a935a2c20400996d665434ec9e17
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree.
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: ae556c6a49d47208e4cbc70efab3dfd5bb2ac309
https://github.com/qemu/qemu/commit/ae556c6a49d47208e4cbc70efab3dfd5bb2ac309
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also for CMPRB, following review comments :
Replaced repetition of arithmetic right shifting (tcg_gen_shri_i32) followed
by extraction of last 8 bits (tcg_gen_ext8u_i32) with extraction of the required
bits using offsets (tcg_gen_extract_i32).
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 948e257c48cf8e387e12b81f4b96195d52b68455
https://github.com/qemu/qemu/commit/948e257c48cf8e387e12b81f4b96195d52b68455
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
Log Message:
-----------
target/ppc: Move logical fixed-point instructions to decodetree.
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 21b5f5464f97f68f025c86330146d038d2ee79ad
https://github.com/qemu/qemu/commit/21b5f5464f97f68f025c86330146d038d2ee79ad
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/mem_helper.c
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VMX storage access instructions to decodetree
Moving the following instructions to decodetree specification :
{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r} : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 664eb39ec94d6fc6e8a96949b0a27deb0c32f50d
https://github.com/qemu/qemu/commit/664eb39ec94d6fc6e8a96949b0a27deb0c32f50d
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VMX integer logical instructions to decodetree.
Moving the following instructions to decodetree specification:
v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form
The changes were verified by validating that the tcp ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 687a30ad3c0f219bb372d806575eb47fae0cd27c
https://github.com/qemu/qemu/commit/687a30ad3c0f219bb372d806575eb47fae0cd27c
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VMX integer max/min instructions to decodetree.
Moving the following instructions to decodetree specification :
v{max, min}{u, s}{b, h, w, d} : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: a7138e28a242680ae25b52ed44842cde235103f0
https://github.com/qemu/qemu/commit/a7138e28a242680ae25b52ed44842cde235103f0
Author: Glenn Miles <mil...@linux.vnet.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/machine.c
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add new hflags to support BHRB
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be recorded. Checking each of these fields with each
branch instruction using jitted code would lead to a significant
decrease in performance.
Therefore, it was decided that BHRB configuration bits that are
not expected to change frequently should have their state summarized
in an hflag so that the amount of checking done by jitted code can
be reduced.
This commit contains the changes for summarizing the state of the
following register fields in the HFLAGS_BHRB_ENABLE hflag:
MMCR0[FCP] - Determines if BHRB recording is frozen in the
problem state
MMCR0[FCPC] - A modifier for MMCR0[FCP]
MMCRA[BHRBRD] - Disables all BHRB recording for a thread
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Glenn Miles <mil...@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 4de4a4705f234861176b32292374021ee96e004e
https://github.com/qemu/qemu/commit/4de4a4705f234861176b32292374021ee96e004e
Author: Glenn Miles <mil...@linux.vnet.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
M target/ppc/translate/branch-impl.c.inc
Log Message:
-----------
target/ppc: Add recording of taken branches to BHRB
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Enabled functionality on P10 processors only due to
performance impact seen with P8 and P9 where it is not
disabled for non problem state branches.
- Added a BHRB buffer for storing branch instruction and
target addresses for taken branches
- Renamed gen_update_cfar to gen_update_branch_history and
added a 'target' parameter to hold the branch target
address and 'inst_type' parameter to use for filtering
- Added TCG code to gen_update_branch_history that stores
data to the BHRB and updates the BHRB offset.
- Added BHRB resource initialization and reset functions
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Glenn Miles <mil...@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 6bfcf1dc239dba752307f0312e8a320470c26655
https://github.com/qemu/qemu/commit/6bfcf1dc239dba752307f0312e8a320470c26655
Author: Glenn Miles <mil...@linux.vnet.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/misc_helper.c
M target/ppc/translate.c
A target/ppc/translate/bhrb-impl.c.inc
Log Message:
-----------
target/ppc: Add clrbhrb and mfbhrbe instructions
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem state).
A new function, helper_mmcr0_facility_check, was added for
checking MMCR0[BHRBA] and raising a facility_unavailable exception
if required.
NOTE: For P8 and P9, due to a performance issue, branch history will
not be kept, but the instructions will be allowed to execute
as normal with the exception that the mfbhrbe instruction will
always return a zero value.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Glenn Miles <mil...@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: dabd6d3c3ae1ba52662d2056a8d59b01d9ee8e24
https://github.com/qemu/qemu/commit/dabd6d3c3ae1ba52662d2056a8d59b01d9ee8e24
Author: Glenn Miles <mil...@linux.vnet.ibm.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Add migration support for BHRB
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Glenn Miles <mil...@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 21cfc36a6c2190932ea55edbce241e6b6b7b9c8f
https://github.com/qemu/qemu/commit/21cfc36a6c2190932ea55edbce241e6b6b7b9c8f
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: larx/stcx generation need only apply DEF_MEMOP() once
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: c10c6ce032959b8b4ada8b8d755a10cad7b5f1a7
https://github.com/qemu/qemu/commit/c10c6ce032959b8b4ada8b8d755a10cad7b5f1a7
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove redundant MEMOP_GET_SIZE macro
There is a memop_size() function for this.
Reviewed-by: BALATON Zoltan <bala...@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: cce7aee8dd934dca3040eb8ea1ad1973701d7c96
https://github.com/qemu/qemu/commit/cce7aee8dd934dca3040eb8ea1ad1973701d7c96
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Make checkstop actually stop the system
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 9728fb5c22a51b5f2f65ba36fdcd8fd0999be6fc
https://github.com/qemu/qemu/commit/9728fb5c22a51b5f2f65ba36fdcd8fd0999be6fc
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: improve checkstop logging
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 45693f94dd11f26b673541c0c9a270f8462d8633
https://github.com/qemu/qemu/commit/45693f94dd11f26b673541c0c9a270f8462d8633
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/misc-impl.c.inc
Log Message:
-----------
target/ppc: Implement attn instruction on BookS 64-bit processors
attn is an implementation-specific instruction that on POWER (and G5/
970) can be enabled with a HID bit (disabled = illegal), and executing
it causes the host processor to stop and the service processor to be
notified. Generally used for debugging.
Implement attn and make it checkstop the system, which should be good
enough for QEMU debugging.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e89294b27e6fb4e976c08768a4a2ca0e8820a4ca
https://github.com/qemu/qemu/commit/e89294b27e6fb4e976c08768a4a2ca0e8820a4ca
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: BookE DECAR SPR is 32-bit
The DECAR SPR is 32-bits width.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 1cbcbcb8d6f10d742aa7cf6ad7bc768492e6407e
https://github.com/qemu/qemu/commit/1cbcbcb8d6f10d742aa7cf6ad7bc768492e6407e
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add PPR32 SPR
PPR32 provides access to the upper half of PPR.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 5fa7efe4730586648412f59f13bd370c40f372ff
https://github.com/qemu/qemu/commit/5fa7efe4730586648412f59f13bd370c40f372ff
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: add helper to write per-LPAR SPRs
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e5c2ac9dc1da8cfb7830a44cb4dcb94ba983c1ad
https://github.com/qemu/qemu/commit/e5c2ac9dc1da8cfb7830a44cb4dcb94ba983c1ad
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Add SMT support to simple SPRs
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 4d2b0ad32a593ac24757b66f64efe2fb84161345
https://github.com/qemu/qemu/commit/4d2b0ad32a593ac24757b66f64efe2fb84161345
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add SMT support to PTCR SPR
PTCR is a per-core register.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: c9d5aedf40cfa0d68a6a4c020d14f8e6116a369e
https://github.com/qemu/qemu/commit/c9d5aedf40cfa0d68a6a4c020d14f8e6116a369e
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Implement LDBAR, TTR SPRs
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 2736432ffc30b74fc72858854e62b62253b685ff
https://github.com/qemu/qemu/commit/2736432ffc30b74fc72858854e62b62253b685ff
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/misc_helper.c
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Implement SPRC/SPRD SPRs
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 0dfe59fe77ed571f23aefb70a3a226c3e1779862
https://github.com/qemu/qemu/commit/0dfe59fe77ed571f23aefb70a3a226c3e1779862
Author: Nicholas Piggin <npig...@gmail.com>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/translate/processor-ctrl-impl.c.inc
Log Message:
-----------
target/ppc: add SMT support to msgsnd broadcast
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 41e9a098d175fdaeb025fe39be940940d1edd979
https://github.com/qemu/qemu/commit/41e9a098d175fdaeb025fe39be940940d1edd979
Author: Dr. David Alan Gilbert <d...@treblig.org>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu-hash32.c
Log Message:
-----------
target/ppc: Remove unused struct 'mmu_ctx_hash32'
I think it's use was removed by
Commit 5883d8b296 ("mmu-hash*: Don't use full ppc_hash{32,
64}_translate() path for get_phys_page_debug()")
Reviewed-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Dr. David Alan Gilbert <d...@treblig.org>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 2b92822acc3e8cb7ce22c75a115b53219f0458b9
https://github.com/qemu/qemu/commit/2b92822acc3e8cb7ce22c75a115b53219f0458b9
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove unused helper_rac()
The helper_rac function is defined but not used, remove it.
Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 3f520078deba9b5aaf5f5896c5b836341f5fc652
https://github.com/qemu/qemu/commit/3f520078deba9b5aaf5f5896c5b836341f5fc652
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Move calculation of a value closer to its usage in booke tlb
checks
In mmubooke_check_tlb() and mmubooke206_check_tlb() prot2 is
calculated first but only used after an unrelated check that can
return before tha value is used. Move the calculation after the check,
closer to where it is used, to keep them together and avoid computing
it when not needed.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 750fbe334237e03056fda45ab36c8b155f65d1b5
https://github.com/qemu/qemu/commit/750fbe334237e03056fda45ab36c8b155f65d1b5
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove unneeded local variable from booke tlb checks
In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
value of prot2 directly to the destination, no need to have a separate
local variable for it.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: fef517cd8a3fb6baba15405448c4cb1dcd1b677a
https://github.com/qemu/qemu/commit/fef517cd8a3fb6baba15405448c4cb1dcd1b677a
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Simplify checking for real mode in get_physical_address_wtlb()
In get_physical_address_wtlb() the real_mode flag depends on either
the MSR[IR] or MSR[DR] bit depending on access_type. Extract just the
needed bit in a more straight forward way instead of doing unnecessary
computation.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: cfd5c128320ab36ca5fa330a9e1968bf4d3cd2b6
https://github.com/qemu/qemu/commit/cfd5c128320ab36ca5fa330a9e1968bf4d3cd2b6
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Drop cases for unimplemented MPC8xx MMU
Drop MPC8xx cases from get_physical_address_wtlb() and ppc_jumbo_xlate().
The default case would still catch this and abort the same way and
there is still a warning about it in ppc_tlb_invalidate_all() which is
called in ppc_cpu_reset_hold() so likely we never get here but to make
sure add a case to ppc_xlate() to the same effect.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 269d6f006b855266bb60b3e027a143ae1a654179
https://github.com/qemu/qemu/commit/269d6f006b855266bb60b3e027a143ae1a654179
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Introduce mmu6xx_get_physical_address()
Repurpose get_segment_6xx_tlb() to do the whole address translation
for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
renaming it to match other similar functions. These are only called
once together so no need to keep these separate functions and
combining them simplifies the caller allowing further restructuring.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: f1418bdeb09d201ea636d061fa6edf1175074a09
https://github.com/qemu/qemu/commit/f1418bdeb09d201ea636d061fa6edf1175074a09
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Move else branch to avoid large if block in
mmu6xx_get_physical_address()
In mmu6xx_get_physical_address() we have a large if block with a two
line else branch that effectively returns. Invert the condition and
move the else there to allow deindenting the large if block to make
the flow easier to follow.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 0af20f35d254bc87689a9d5ab2c5e45a677467dc
https://github.com/qemu/qemu/commit/0af20f35d254bc87689a9d5ab2c5e45a677467dc
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Move some debug logging in ppc6xx_tlb_check()
Move the debug logging within ppc6xx_tlb_check() from after its only
call to simplify the caller.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: f3f66a315714a0bf10c1b82df3324834c9b484fc
https://github.com/qemu/qemu/commit/f3f66a315714a0bf10c1b82df3324834c9b484fc
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Eliminate ret from mmu6xx_get_physical_address()
Return directly, which is simpler than dragging a return value through
multpile if and else blocks.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 279fe98d0d3057daa4045faa6e2119288d7b7f07
https://github.com/qemu/qemu/commit/279fe98d0d3057daa4045faa6e2119288d7b7f07
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Split out BookE xlate cases before checking real mode
BookE does not have real mode so split off and handle it first in
get_physical_address_wtlb() before checking for real mode for other
MMU models.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 549685161da1d4c948eee0a4a3da6f9a6b879e83
https://github.com/qemu/qemu/commit/549685161da1d4c948eee0a4a3da6f9a6b879e83
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Split off real mode cases in get_physical_address_wtlb()
The real mode handling is identical in the remaining switch cases.
Split off these common real mode cases into a separate conditional to
leave only the else branches in the switch that are different.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 77d9607d711b723b4873764051c4d5dc84894422
https://github.com/qemu/qemu/commit/77d9607d711b723b4873764051c4d5dc84894422
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Inline and remove check_physical()
This function just does two assignments and and unnecessary check that
is always true so inline it in the only caller left and remove it.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 47bededc299c5cd0cbbf10660405d7076361fbaa
https://github.com/qemu/qemu/commit/47bededc299c5cd0cbbf10660405d7076361fbaa
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Fix misindented qemu_log_mask() calls
Fix several qemu_log_mask() calls that are misindented.
Acked-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 9e9ca54cdb493721f8444030e6dcf680400c8d0b
https://github.com/qemu/qemu/commit/9e9ca54cdb493721f8444030e6dcf680400c8d0b
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Deindent ppc_jumbo_xlate()
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.
Acked-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: f178e4f8949ec75d0e1e34f9b1ace646d1e6a031
https://github.com/qemu/qemu/commit/f178e4f8949ec75d0e1e34f9b1ace646d1e6a031
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Replace hard coded constants in ppc_jumbo_xlate()
The "2" in booke206_update_mas_tlb_miss() call corresponds to
MMU_INST_FETCH which is the value of access_type in this branch;
mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
code access so using MMU_DATA_LOAD here seems wrong so replace it with
access_type here as well that yields the same result. This also makes
these calls the same as the data access branch further down.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 5cc867a679d4b5032284d30d22dad8e81195e60d
https://github.com/qemu/qemu/commit/5cc867a679d4b5032284d30d22dad8e81195e60d
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Don't use mmu_ctx_t for mmu40x_get_physical_address()
mmu40x_get_physical_address() only uses the raddr and prot fields from
mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: ecff3394a81f536fc537878cb9bfbc48b3f8690e
https://github.com/qemu/qemu/commit/ecff3394a81f536fc537878cb9bfbc48b3f8690e
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Don't use mmu_ctx_t in mmubooke_get_physical_address()
mmubooke_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e8a9c0fbffe80946ae1a6004b77a18a030cce6f1
https://github.com/qemu/qemu/commit/e8a9c0fbffe80946ae1a6004b77a18a030cce6f1
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Don't use mmu_ctx_t in mmubooke206_get_physical_address()
mmubooke206_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: aa30aa7d8e9232cb1bfdc4feb12b03095c2ff519
https://github.com/qemu/qemu/commit/aa30aa7d8e9232cb1bfdc4feb12b03095c2ff519
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove BookE from direct store handling
As BookE never returns -4 we can drop BookE from the direct store case
in ppc_jumbo_xlate().
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: ba91e5d0276607fd6f862b498603f94c16ec0e07
https://github.com/qemu/qemu/commit/ba91e5d0276607fd6f862b498603f94c16ec0e07
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Split off BookE handling from ppc_jumbo_xlate()
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: aa20e1c8c642a1986f8e949af311d9bd2ee70f8e
https://github.com/qemu/qemu/commit/aa20e1c8c642a1986f8e949af311d9bd2ee70f8e
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Simplify ppc_booke_xlate() part 1
Move setting error_code that appears in every case out in front and
hoist the common fall through case for BOOKE206 as well which allows
removing the nested switches.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: b18489b326c0677ed7d0178361a65df867b4a16f
https://github.com/qemu/qemu/commit/b18489b326c0677ed7d0178361a65df867b4a16f
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Simplify ppc_booke_xlate() part 2
Merge the code fetch and data access cases in a common switch.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: c29f808af5b14d24ec8591be46c37441c7c15663
https://github.com/qemu/qemu/commit/c29f808af5b14d24ec8591be46c37441c7c15663
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Split off real mode handling from get_physical_address_wtlb()
Add ppc_real_mode_xlate() to handle real mode translation and allow
removing this case from ppc_jumbo_xlate().
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 58b0132553139b481a4b6ea1c597465152381f66
https://github.com/qemu/qemu/commit/58b0132553139b481a4b6ea1c597465152381f66
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Split off 40x cases from ppc_jumbo_xlate()
Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx
in ppc_jumbo_xlate() now.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 6b9ea7f3452ecf58582392eefae85db24fc6003f
https://github.com/qemu/qemu/commit/6b9ea7f3452ecf58582392eefae85db24fc6003f
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/internal.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Transform ppc_jumbo_xlate() into ppc_6xx_xlate()
Now that only 6xx cases left in ppc_jumbo_xlate() we can change it
to ppc_6xx_xlate() also removing get_physical_address_wtlb().
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 306b5320307d13e95e1d43b585879cb56b163f66
https://github.com/qemu/qemu/commit/306b5320307d13e95e1d43b585879cb56b163f66
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/internal.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Move mmu_ctx_t type to mmu_common.c
Remove mmu_ctx_t definition from internal.h as this type is only used
within mmu_common.c.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 5fd257f5994335c9446b0fa8b6cfd6102c2f74ca
https://github.com/qemu/qemu/commit/5fd257f5994335c9446b0fa8b6cfd6102c2f74ca
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M hw/ppc/pegasos2.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove id_tlbs flag from CPU env
This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 581eea5d656b73c6532109f4ced4c73fd4e5fd47
https://github.com/qemu/qemu/commit/581eea5d656b73c6532109f4ced4c73fd4e5fd47
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Split off common embedded TLB init
Several 4xx CPUs and e200 share the same TLB settings enclosed in an
ifdef. Split it off in a common function to reduce code duplication
and the number of ifdefs.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e89b0629b99e3df96ef1c190139f77169c58d27b
https://github.com/qemu/qemu/commit/e89b0629b99e3df96ef1c190139f77169c58d27b
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu-hash32.c
Log Message:
-----------
target/ppc/mmu-hash32.c: Drop a local variable
In ppc_hash32_xlate() the value of need_prop is checked in two places
but precalculating it does not help because when we reach the first
check we always return and not reach the second place so the value
will only be used once. We can drop the local variable and calculate
it when needed, which makes these checks using it similar to other
places with such checks.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: 950251ee7b459d160fd3adfa2792326aa29b5d6c
https://github.com/qemu/qemu/commit/950251ee7b459d160fd3adfa2792326aa29b5d6c
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc/mmu-radix64.c: Drop a local variable
The value is only used once so no need to introduce a local variable
for it.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: cd1038ec1d316aeca52a0c5d18da055d5aa014c9
https://github.com/qemu/qemu/commit/cd1038ec1d316aeca52a0c5d18da055d5aa014c9
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/internal.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Add a function to check for page protection bit
Checking if a page protection bit is set for a given access type is a
common operation. Add a function to avoid repeating the same check at
multiple places. As this relies on access type and page protection bit
values having certain relation also add an assert to ensure that this
assumption holds.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e7baac649bb3d9d72a3e79fc43e360d7ac99aead
https://github.com/qemu/qemu/commit/e7baac649bb3d9d72a3e79fc43e360d7ac99aead
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/meson.build
A target/ppc/mmu-booke.c
A target/ppc/mmu-booke.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Move out BookE and related MMU functions from mmu_common.c
Add a new mmu-booke.c file for BookE and related MMU bits from
mmu_common.c.
Acked-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: e48fb4c590a23d81ee1d2f09ee9bcf5dd5f98e43
https://github.com/qemu/qemu/commit/e48fb4c590a23d81ee1d2f09ee9bcf5dd5f98e43
Author: BALATON Zoltan <bala...@eik.bme.hu>
Date: 2024-05-24 (Fri, 24 May 2024)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot()
The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
pp_check() in mmu_common.c, merge these to remove duplicated code.
Define the common function as static lnline otherwise exporting the
function from mmu-hash32.c would stop the compiler inlining it which
results in slightly lower performance.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
[np: move ppc_hash32_pp_prot inline without changing it]
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Commit: ffdd099a782556b9ead26551a6f1d070a595306d
https://github.com/qemu/qemu/commit/ffdd099a782556b9ead26551a6f1d070a595306d
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2024-05-23 (Thu, 23 May 2024)
Changed paths:
M accel/tcg/cputlb.c
M docs/devel/multi-thread-tcg.rst
M hw/ppc/pegasos2.c
M hw/ppc/spapr.c
M include/exec/exec-all.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/internal.h
M target/ppc/kvm.c
M target/ppc/machine.c
M target/ppc/mem_helper.c
M target/ppc/meson.build
M target/ppc/misc_helper.c
M target/ppc/mmu-book3s-v3.h
A target/ppc/mmu-booke.c
A target/ppc/mmu-booke.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/spr_common.h
M target/ppc/translate.c
A target/ppc/translate/bhrb-impl.c.inc
M target/ppc/translate/branch-impl.c.inc
M target/ppc/translate/fixedpoint-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
A target/ppc/translate/misc-impl.c.inc
M target/ppc/translate/processor-ctrl-impl.c.inc
M target/ppc/translate/storage-ctrl-impl.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
Merge tag 'pull-ppc-for-9.1-1-20240524-1' of https://gitlab.com/npiggin/qemu
into staging
*** NOTE ***
This replaces the previous PR for tags/pull-ppc-for-9.1-1-20240524
* Fix an interesting TLB invalidate race
* Implement more instructions with decodetree
* Add the POWER8/9/10 BHRB facility
* Add missing instructions, registers, SMT support
* First round of a big MMU xlate cleanup
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# gpg: Signature made Thu 23 May 2024 04:48:11 PM PDT
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npig...@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.1-1-20240524-1' of https://gitlab.com/npiggin/qemu: (72
commits)
target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot()
target/ppc: Move out BookE and related MMU functions from mmu_common.c
target/ppc: Add a function to check for page protection bit
target/ppc/mmu-radix64.c: Drop a local variable
target/ppc/mmu-hash32.c: Drop a local variable
target/ppc: Split off common embedded TLB init
target/ppc: Remove id_tlbs flag from CPU env
target/ppc: Move mmu_ctx_t type to mmu_common.c
target/ppc: Transform ppc_jumbo_xlate() into ppc_6xx_xlate()
target/ppc: Split off 40x cases from ppc_jumbo_xlate()
target/ppc: Split off real mode handling from get_physical_address_wtlb()
target/ppc: Simplify ppc_booke_xlate() part 2
target/ppc: Simplify ppc_booke_xlate() part 1
target/ppc: Split off BookE handling from ppc_jumbo_xlate()
target/ppc: Remove BookE from direct store handling
target/ppc: Don't use mmu_ctx_t in mmubooke206_get_physical_address()
target/ppc: Don't use mmu_ctx_t in mmubooke_get_physical_address()
target/ppc: Don't use mmu_ctx_t for mmu40x_get_physical_address()
target/ppc: Replace hard coded constants in ppc_jumbo_xlate()
target/ppc: Deindent ppc_jumbo_xlate()
...
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/70581940cabc...ffdd099a7825
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