Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e6e903db6a5e960e595f9f1fd034adb942dd9508
https://github.com/qemu/qemu/commit/e6e903db6a5e960e595f9f1fd034adb942dd9508
Author: Michael Vogt <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M linux-user/ioctls.h
Log Message:
-----------
linux-user: Add ioctl for BLKBSZSET
Tiny patch to add the ioctl wrapper definition for BLKBSZSET.
Signed-off-by: Michael Vogt <[email protected]>
Message-Id: <[email protected]>
Commit: fa9079a86d94c202c316c97ca2eb61ca3e763907
https://github.com/qemu/qemu/commit/fa9079a86d94c202c316c97ca2eb61ca3e763907
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix ARRAY8
Follow the Oracle Sparc 2015 implementation note and bound
the input value of N to 5 from the lower 3 bits of rs2.
Spell out all of the intermediate values, matching the diagram
in the manual. Fix extraction of upper_x and upper_y for N=0.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 43db5838022a32752a27e64de6599b8dc427ba9f
https://github.com/qemu/qemu/commit/43db5838022a32752a27e64de6599b8dc427ba9f
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Rewrite gen_edge
Drop the tables and compute the left and right edges directly.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 04d5bf30419412cfbf984e90938b411e22fd8916
https://github.com/qemu/qemu/commit/04d5bf30419412cfbf984e90938b411e22fd8916
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Fix do_dc
Apply DFPREG to compute the register number.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b5c960470d0d7a976aa83e6e3a9b0fdc1d83c7cd
https://github.com/qemu/qemu/commit/b5c960470d0d7a976aa83e6e3a9b0fdc1d83c7cd
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Fix helper_fmul8ulx16
This operation returns the high 16 bits of a 24-bit multiply
that has been sign-extended to 32 bits.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0bba7572d40d5d3f79dd2392051fe3970a41e9db
https://github.com/qemu/qemu/commit/0bba7572d40d5d3f79dd2392051fe3970a41e9db
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Perform DFPREG/QFPREG in decodetree
Form the proper register decoding from the start.
Because we're removing the translation from the inner-most
gen_load_fpr_* and gen_store_fpr_* routines, this must be
done for all insns at once.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 52f46d4627a3f5ce52636ff6b01895e4fcd5e924
https://github.com/qemu/qemu/commit/52f46d4627a3f5ce52636ff6b01895e4fcd5e924
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Remove gen_dest_fpr_D
Replace with tcg_temp_new_i64.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1210a0367d5e9eca7679d401e422c48b61b421b0
https://github.com/qemu/qemu/commit/1210a0367d5e9eca7679d401e422c48b61b421b0
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Remove cpu_fpr[]
Use explicit loads and stores to env instead.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 28c131a34d402811bdb51a0f289bd975074884bc
https://github.com/qemu/qemu/commit/28c131a34d402811bdb51a0f289bd975074884bc
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Use gvec for VIS1 parallel add/sub
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4fd71d19acd6e05b74927a0b5c4a5b0650e3d6f5
https://github.com/qemu/qemu/commit/4fd71d19acd6e05b74927a0b5c4a5b0650e3d6f5
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M linux-user/elfload.c
M target/sparc/cpu-feature.h.inc
M target/sparc/cpu.c
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FMAf extension
Rearrange PDIST so that do_dddd is general purpose and may
be re-used for FMADDd etc. Add pickNaN and pickNaNMulAdd.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3335a04806d337c69f44a707cdc27515d6c91d84
https://github.com/qemu/qemu/commit/3335a04806d337c69f44a707cdc27515d6c91d84
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/cpu-feature.h.inc
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Add feature bits for VIS 3
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus. For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 015fc6fcdb90034a7551091f8cd9a47ca1bd26b1
https://github.com/qemu/qemu/commit/015fc6fcdb90034a7551091f8cd9a47ca1bd26b1
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement ADDXC, ADDXCcc
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c973b4e8df6e4a7b0080e3a93742a4d56baeb84b
https://github.com/qemu/qemu/commit/c973b4e8df6e4a7b0080e3a93742a4d56baeb84b
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement CMASK instructions
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7837185e40dc8b5e97e33e3fbdf94be0b55ef585
https://github.com/qemu/qemu/commit/7837185e40dc8b5e97e33e3fbdf94be0b55ef585
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement FCHKSM16
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3d50b7287e3c11b769945fd7352788d69b1a5a5e
https://github.com/qemu/qemu/commit/3d50b7287e3c11b769945fd7352788d69b1a5a5e
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1d3ed3d728f81dee4ae87028a8a3e9beb4fa4a17
https://github.com/qemu/qemu/commit/1d3ed3d728f81dee4ae87028a8a3e9beb4fa4a17
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FLCMP
Signed-off-by: Richard Henderson <[email protected]>
Commit: d6ff1ccb45f9b228e20f74f6e6c801c88a2885b2
https://github.com/qemu/qemu/commit/d6ff1ccb45f9b228e20f74f6e6c801c88a2885b2
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement FMEAN16
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bc3f14a9ed777ddab8c8915a9804f9b3ca90839d
https://github.com/qemu/qemu/commit/bc3f14a9ed777ddab8c8915a9804f9b3ca90839d
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FPADD64, FPSUB64
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0d1d3aaf6405f9ecf67af886c06f1f710b046563
https://github.com/qemu/qemu/commit/0d1d3aaf6405f9ecf67af886c06f1f710b046563
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FPADDS, FPSUBS
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 669e077437d5782682e2ac4f1082fcbf102b5680
https://github.com/qemu/qemu/commit/669e077437d5782682e2ac4f1082fcbf102b5680
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fbc5c8d4e8f10fdb780c450aa49b503e6d592cc6
https://github.com/qemu/qemu/commit/fbc5c8d4e8f10fdb780c450aa49b503e6d592cc6
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 298c52f784ac0f6c09a4621609ac9008b7fa15f9
https://github.com/qemu/qemu/commit/298c52f784ac0f6c09a4621609ac9008b7fa15f9
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement LDXEFSR
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 875ce3929aef9d0dcee67b506991ea84e505729b
https://github.com/qemu/qemu/commit/875ce3929aef9d0dcee67b506991ea84e505729b
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement LZCNT
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 09b157e6283d02e02ec9f47d8d4a2fd0cd8612ce
https://github.com/qemu/qemu/commit/09b157e6283d02e02ec9f47d8d4a2fd0cd8612ce
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7d5ebd8ffe241c57d6857ae75b67de6c6af3429c
https://github.com/qemu/qemu/commit/7d5ebd8ffe241c57d6857ae75b67de6c6af3429c
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement PDISTN
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 680af1b4a523cd7f15690cad7afb069e6efbbec0
https://github.com/qemu/qemu/commit/680af1b4a523cd7f15690cad7afb069e6efbbec0
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement UMULXHI
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 029b0283dfe64c38e48f9dd9aad0dc6d254c4ea4
https://github.com/qemu/qemu/commit/029b0283dfe64c38e48f9dd9aad0dc6d254c4ea4
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement XMULX
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: deadbb14ba7a9cbdabbd102f7bf470c0baf9f25a
https://github.com/qemu/qemu/commit/deadbb14ba7a9cbdabbd102f7bf470c0baf9f25a
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M linux-user/elfload.c
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Enable VIS3 feature bit
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 68a414e99d438ff5e3e598d140c8f81638a8ea9e
https://github.com/qemu/qemu/commit/68a414e99d438ff5e3e598d140c8f81638a8ea9e
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M linux-user/elfload.c
M target/sparc/cpu-feature.h.inc
M target/sparc/cpu.c
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement IMA extension
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 90b1433da8d51ecf0ab36d4c61eec949ee2fffbb
https://github.com/qemu/qemu/commit/90b1433da8d51ecf0ab36d4c61eec949ee2fffbb
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/cpu-feature.h.inc
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Add feature bit for VIS4
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b2b48493362b9f77ca66fffb1464f7fc5a32c6e9
https://github.com/qemu/qemu/commit/b2b48493362b9f77ca66fffb1464f7fc5a32c6e9
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FALIGNDATAi
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b99c1bbddd86d170029c3e7ad45bec55d603b927
https://github.com/qemu/qemu/commit/b99c1bbddd86d170029c3e7ad45bec55d603b927
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b3c934dd3457810b5c0810b0d85cf58dda53d8cd
https://github.com/qemu/qemu/commit/b3c934dd3457810b5c0810b0d85cf58dda53d8cd
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
target/sparc: Implement VIS4 comparisons
VIS4 completes the set, adding missing signed 8-bit ops
and missing unsigned 16 and 32-bit ops.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: db11dfea83e35c534fef8a86603b72354be9d71b
https://github.com/qemu/qemu/commit/db11dfea83e35c534fef8a86603b72354be9d71b
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement FPMIN, FPMAX
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 56f2ef9c7958320d574448f555cc3a82e500c485
https://github.com/qemu/qemu/commit/56f2ef9c7958320d574448f555cc3a82e500c485
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement SUBXC, SUBXCcc
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6fbc032cbc83ba80009c4a2a18e4d5578bc9ba35
https://github.com/qemu/qemu/commit/6fbc032cbc83ba80009c4a2a18e4d5578bc9ba35
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement MWAIT
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: eeb3f592cb364f9d5c70c5525fd90e43b216012d
https://github.com/qemu/qemu/commit/eeb3f592cb364f9d5c70c5525fd90e43b216012d
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/asi.h
M target/sparc/ldst_helper.c
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Implement monitor ASIs
Ignore the "monitor" portion and treat them the same
as their base ASIs.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b12b72274320ce3ee516d963efd48766163cb240
https://github.com/qemu/qemu/commit/b12b72274320ce3ee516d963efd48766163cb240
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Enable VIS4 feature bit
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 535ad16c5d668f6185be2f88c6c82bf8e452c45d
https://github.com/qemu/qemu/commit/535ad16c5d668f6185be2f88c6c82bf8e452c45d
Author: Richard Henderson <[email protected]>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M linux-user/elfload.c
M linux-user/ioctls.h
M target/sparc/asi.h
M target/sparc/cpu-feature.h.inc
M target/sparc/cpu.c
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/insns.decode
M target/sparc/ldst_helper.c
M target/sparc/translate.c
M target/sparc/vis_helper.c
Log Message:
-----------
Merge tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu into staging
target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions
linux-user: Add ioctl for BLKBSZSET
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 05 Jun 2024 09:13:12 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[ultimate]
* tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu: (38 commits)
target/sparc: Enable VIS4 feature bit
target/sparc: Implement monitor ASIs
target/sparc: Implement MWAIT
target/sparc: Implement SUBXC, SUBXCcc
target/sparc: Implement FPMIN, FPMAX
target/sparc: Implement VIS4 comparisons
target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS
target/sparc: Implement FALIGNDATAi
target/sparc: Add feature bit for VIS4
target/sparc: Implement IMA extension
target/sparc: Enable VIS3 feature bit
target/sparc: Implement XMULX
target/sparc: Implement UMULXHI
target/sparc: Implement PDISTN
target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
target/sparc: Implement LZCNT
target/sparc: Implement LDXEFSR
target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8
target/sparc: Implement FPADDS, FPSUBS
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/f1572ab94738...535ad16c5d66
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