Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ee48fef06c034ff245db9e553dcf0f1262f97bd2
https://github.com/qemu/qemu/commit/ee48fef06c034ff245db9e553dcf0f1262f97bd2
Author: Cédric Le Goater <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Reintroduce "dram-base" property for AST2700
The Aspeed SMC device model use to have a 'sdram_base' property. It
was removed by commit d177892d4a48 ("aspeed/smc: Remove unused
"sdram-base" property") because previous changes simplified the DMA
transaction model to use an offset in RAM and not the physical
address.
The AST2700 SoC has larger address space (64-bit) and a new register
DMA DRAM Side Address High Part (0x7C) is introduced to deal with the
high bits of the DMA address. To be able to compute the offset of the
DMA transaction, as done on the other SoCs, we will need to know where
the DRAM is mapped in the address space. Re-introduce a "dram-base"
property to hold this value.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Jamin Lin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8db36a4f74ea97c2d7b5cd21515cd61c3749f39d
https://github.com/qemu/qemu/commit/8db36a4f74ea97c2d7b5cd21515cd61c3749f39d
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/watchdog/wdt_aspeed.c
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
aspeed/wdt: Add AST2700 support
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: f944890dfd4222f091cea8680281e0bf7114f721
https://github.com/qemu/qemu/commit/f944890dfd4222f091cea8680281e0bf7114f721
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
A hw/misc/aspeed_sli.c
M hw/misc/meson.build
M hw/misc/trace-events
A include/hw/misc/aspeed_sli.h
Log Message:
-----------
aspeed/sli: Add AST2700 support
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: c7f3b1a042e7bdb105972185d1baf27901bd498e
https://github.com/qemu/qemu/commit/c7f3b1a042e7bdb105972185d1baf27901bd498e
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/misc/aspeed_sdmc.c
Log Message:
-----------
aspeed/sdmc: remove redundant macros
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 39e6dc52a851e750e059965504eac71b727ab1ca
https://github.com/qemu/qemu/commit/39e6dc52a851e750e059965504eac71b727ab1ca
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/misc/aspeed_sdmc.c
Log Message:
-----------
aspeed/sdmc: fix coding style
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 3347b9a1f7f74513dad91a7c4bee74903e787bf9
https://github.com/qemu/qemu/commit/3347b9a1f7f74513dad91a7c4bee74903e787bf9
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/misc/aspeed_sdmc.c
M include/hw/misc/aspeed_sdmc.h
Log Message:
-----------
aspeed/sdmc: Add AST2700 support
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
aspeed_2700_sdmc and class with read/write operation and
reset handlers.
Define DRAMC necessary protected registers and
unprotected registers for AST2700 and increase
the register set to 0x1000.
Add unlocked property to change controller protected status.
Incrementing the version of vmstate to 2.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: d108dfea1967d57d462a0d4af344524fcf9cd23e
https://github.com/qemu/qemu/commit/d108dfea1967d57d462a0d4af344524fcf9cd23e
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: correct device description
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 3a6c0f0e9d71e9a5f5bf4d5d31693a2f0cdd71c1
https://github.com/qemu/qemu/commit/3a6c0f0e9d71e9a5f5bf4d5d31693a2f0cdd71c1
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: support dma start length and 1 byte length unit
DMA length is from 1 byte to 32MB for AST2600 and AST10x0
and DMA length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte
data for AST2600 and AST10x0 and 4 bytes data for AST2500.
To support all ASPEED SOCs, adds dma_start_length parameter to store
the start length, add helper routines function to compute the dma length
and update DMA_LENGTH mask to "1FFFFFF" to support dma 1 byte
length unit for AST2600 and AST1030.
Currently, only supports dma length 4 bytes aligned.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 6330be8da44cf11e429197187e814299eff881cd
https://github.com/qemu/qemu/commit/6330be8da44cf11e429197187e814299eff881cd
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
M hw/ssi/trace-events
Log Message:
-----------
aspeed/smc: support 64 bits dma dram address
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
address, new features and update trace-event
to support 64 bits dram address.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 0559e60669bae9c047cd5cf6f9be38ea7ced39b2
https://github.com/qemu/qemu/commit/0559e60669bae9c047cd5cf6f9be38ea7ced39b2
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: support different memory region ops for SMC flash region
It set "aspeed_smc_flash_ops" struct which containing
read and write callbacks to be used when I/O is performed
on the SMC flash region. And it set the valid max_access_size 4
by default for all ASPEED SMC models.
However, the valid max_access_size 4 only support 32 bits CPUs.
To support all ASPEED SMC model, introduce a new
"const MemoryRegionOps *" attribute in AspeedSMCClass and
use it in aspeed_smc_flash_realize function.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: bdb3748dba309cba0bf71ca6ea4521911953b825
https://github.com/qemu/qemu/commit/bdb3748dba309cba0bf71ca6ea4521911953b825
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Add AST2700 support
AST2700 fmc/spi controller's address decoding unit is 64KB
and only bits [31:16] are used for decoding. Introduce seg_to_reg
and reg_to_seg handlers for ast2700 fmc/spi controller.
In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler.
AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new
"aspeed_2700_smc_flash_ops" and set its valid "max_access_size"
8 for 64 bits data format access.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: e7c8106d48b8f3719415c9fedbcf2d2b1897c608
https://github.com/qemu/qemu/commit/e7c8106d48b8f3719415c9fedbcf2d2b1897c608
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/misc/aspeed_scu.c
M hw/misc/trace-events
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
aspeed/scu: Add AST2700 support
AST2700 have two SCU controllers which are SCU and SCUIO.
Both SCU and SCUIO registers are not compatible previous SOCs
, introduces new registers and adds ast2700 scu, sucio class init handler.
The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and
the pclk divider selection of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[clg: Fixed spelling : Unhandeled -> Unhandled ]
Commit: d831c5fd868225882c5297b34a241929c267be13
https://github.com/qemu/qemu/commit/d831c5fd868225882c5297b34a241929c267be13
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
A hw/intc/aspeed_intc.c
M hw/intc/meson.build
M hw/intc/trace-events
A include/hw/intc/aspeed_intc.h
Log Message:
-----------
aspeed/intc: Add AST2700 support
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers.
So far, this model only supports GICINT128 to GICINT136.
It creates 9 GICINT or-gates to connect 32 interrupts sources
from GICINT128 to GICINT136 as IRQ GPIO-OUTPUT pins.
Then, this model registers IRQ handler with its IRQ GPIO-INPUT pins which
connect to GICINT or-gates. And creates 9 GICINT IRQ GPIO-OUTPUT pins which
connect to GIC device with GIC IRQ 128 to 136.
If one interrupt source from GICINT128 to GICINT136
set irq, the OR-GATE irq callback function is called and set irq to INTC by
OR-GATE GPIO-OUTPUT pins. Then, the INTC irq callback function is called and
set irq to GIC by its GICINT IRQ GPIO-OUTPUT pins. Finally, the GIC irq
callback function is called and set irq to CPUs and
CPUs execute Interrupt Service Routine (ISR).
Block diagram of GICINT132:
GICINT132
ETH1 +-----------+
+-------->+0 3|
ETH2 | 4|
+-------->+1 5|
ETH3 | 6|
+-------->+2 19| INTC
GIC
UART0 | 20| +--------------------------+
+-------->+7 21| | |
+--------------+
UART1 | 22| |orgate0 +---->
output_pin0+----------->+GIC128 |
+-------->+8 23| | | |
|
UART2 | 24| |orgate1 +---->
output_pin1+----------->+GIC129 |
+-------->+9 25| | | |
|
UART3 | 26| |orgate2 +---->
output_pin2+----------->+GIC130 |
+--------->10 27| | | |
|
UART5 | 28| |orgate3 +---->
output_pin3+----------->+GIC131 |
+-------->+11 29| | | |
|
UART6 | +----------->+orgate4 +---->
output_pin4+----------->+GIC132 |
+-------->+12 30| | | |
|
UART7 | 31| |orgate5 +---->
output_pin5+----------->+GIC133 |
+-------->+13 | | | |
|
UART8 | OR[0:31] | |orgate6 +---->
output_pin6+----------->+GIC134 |
---------->14 | | | |
|
UART9 | | |orgate7 +---->
output_pin7+----------->+GIC135 |
--------->+15 | | | |
|
UART10 | | |orgate8 +---->
output_pin8+----------->+GIC136 |
--------->+16 | | |
+--------------+
UART11 | | +--------------------------+
+-------->+17 |
UART12 | |
+--------->18 |
| |
| |
| |
+-----------+
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[clg: Fixed class_size in TYPE_ASPEED_INTC definition ]
Commit: 5dd883ab0635c9f715c77cc32622e458a0724581
https://github.com/qemu/qemu/commit/5dd883ab0635c9f715c77cc32622e458a0724581
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
A hw/arm/aspeed_ast27x0.c
M hw/arm/meson.build
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed/soc: Add AST2700 support
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 92707992103effc3e4f6f8a03da59e627acc1e34
https://github.com/qemu/qemu/commit/92707992103effc3e4f6f8a03da59e627acc1e34
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Add an AST2700 eval board
AST2700 CPU is ARM Cortex-A35 which is 64 bits.
Add TARGET_AARCH64 to build this machine.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 7436db1063bbfecc2e498a7d795613b33312d665
https://github.com/qemu/qemu/commit/7436db1063bbfecc2e498a7d795613b33312d665
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed/soc: fix incorrect dram size for AST2700
AST2700 dram size calculation is not back compatible AST2600.
According to the DDR capacity hardware behavior,
if users write the data to the address which is beyond the ram size,
it would write the data to the "address % ram_size".
For example:
a. sdram base address "0x4 00000000"
b. sdram size 1 GiB
The available address range is from "0x4 00000000" to "0x4 3FFFFFFF".
If users write 0x12345678 to address "0x5 00000000",
the value of DRAM address 0 (base address 0x4 00000000) will be 0x12345678.
Add aspeed_soc_ast2700_dram_init to calculate the dram size and add
memory I/O whose address range is from "max_ram_size - ram_size" to max_ram_size
and its read/write handler to emulate DDR capacity hardware behavior.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 1478055d3a3940e4d708919b6d83b03ef6474af4
https://github.com/qemu/qemu/commit/1478055d3a3940e4d708919b6d83b03ef6474af4
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M tests/avocado/machine_aspeed.py
Log Message:
-----------
test/avocado/machine_aspeed.py: Add AST2700 test case
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board.
It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os
images to dram first which base address is 0x400000000.
Then, boot and launch 4 cpu cores.
```
qemu-system-aarch64 -machine ast2700-evb
-device loader,force-raw=on,addr=0x400000000,file=workdir/u-boot-nodtb.bin \
-device
loader,force-raw=on,addr=uboot_dtb_load_addr,file=workdir/u-boot.dtb\
-device loader,force-raw=on,addr=0x430000000,file=workdir/bl31.bin\
-device loader,force-raw=on,addr=0x430080000,file=workdir/optee/tee-raw.bin\
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-smp 4 \
-drive file=workdir/image-bmc,format=raw,if=mtd
```
A test image is downloaded from the ASPEED Forked OpenBMC GitHub release
repository :
https://github.com/AspeedTech-BMC/openbmc/releases/
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: b3e8223e48f4a8981232a17ebf48c198829ce191
https://github.com/qemu/qemu/commit/b3e8223e48f4a8981232a17ebf48c198829ce191
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs:aspeed: Add AST2700 Evaluation board
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 5f44521242d2fdfa190206a6be40577a58a71ef9
https://github.com/qemu/qemu/commit/5f44521242d2fdfa190206a6be40577a58a71ef9
Author: Jamin Lin <[email protected]>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add reviewers for ASPEED BMCs
Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin"
to be reviewers of ASPEED BMCs.
Signed-off-by: Jamin Lin <[email protected]>
Signed-off-by: Troy Lee <[email protected]>
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Commit: 79e6ec66ba1067a135394a330fec14b50cf49534
https://github.com/qemu/qemu/commit/79e6ec66ba1067a135394a330fec14b50cf49534
Author: Richard Henderson <[email protected]>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M MAINTAINERS
M docs/system/arm/aspeed.rst
M hw/arm/aspeed.c
A hw/arm/aspeed_ast27x0.c
M hw/arm/meson.build
A hw/intc/aspeed_intc.c
M hw/intc/meson.build
M hw/intc/trace-events
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
A hw/misc/aspeed_sli.c
M hw/misc/meson.build
M hw/misc/trace-events
M hw/ssi/aspeed_smc.c
M hw/ssi/trace-events
M hw/watchdog/wdt_aspeed.c
M include/hw/arm/aspeed_soc.h
A include/hw/intc/aspeed_intc.h
M include/hw/misc/aspeed_scu.h
M include/hw/misc/aspeed_sdmc.h
A include/hw/misc/aspeed_sli.h
M include/hw/ssi/aspeed_smc.h
M include/hw/watchdog/wdt_aspeed.h
M tests/avocado/machine_aspeed.py
Log Message:
-----------
Merge tag 'pull-aspeed-20240617' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Add AST2700 support
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# f8kWMPlXlRpKBYsjvP2aCpoY6CY8bHskdBH7xysM2W1FfKTw3dwZRpt4dgVPxqYj
# KZXiKxzwnC2gGi/wn+EdhZwYy1nNSZYGK8s+jxBXi2UBrwv4PpA=
# =TnR8
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 16 Jun 2024 08:59:49 PM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20240617' of https://github.com/legoater/qemu:
MAINTAINERS: Add reviewers for ASPEED BMCs
docs:aspeed: Add AST2700 Evaluation board
test/avocado/machine_aspeed.py: Add AST2700 test case
aspeed/soc: fix incorrect dram size for AST2700
aspeed: Add an AST2700 eval board
aspeed/soc: Add AST2700 support
aspeed/intc: Add AST2700 support
aspeed/scu: Add AST2700 support
aspeed/smc: Add AST2700 support
aspeed/smc: support different memory region ops for SMC flash region
aspeed/smc: support 64 bits dma dram address
aspeed/smc: support dma start length and 1 byte length unit
aspeed/smc: correct device description
aspeed/sdmc: Add AST2700 support
aspeed/sdmc: fix coding style
aspeed/sdmc: remove redundant macros
aspeed/sli: Add AST2700 support
aspeed/wdt: Add AST2700 support
aspeed/smc: Reintroduce "dram-base" property for AST2700
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/05ad1440b842...79e6ec66ba10
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