Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: e9964c32ba3476db6190556293b754aa50a489d0
https://github.com/qemu/qemu/commit/e9964c32ba3476db6190556293b754aa50a489d0
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M tests/tcg/ppc64/Makefile.target
Log Message:
-----------
tests/tcg: Skip failing ppc64 multi-threaded tests
In Gitlab CI, some ppc64 multi-threaded tcg tests crash when run in the
clang-user job with an assertion failure in glibc that seems to
indicate corruption:
signals: allocatestack.c:223: allocate_stack:
Assertion `powerof2 (pagesize_m1 + 1)' failed.
Disable these tests for now.
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 1a7a31aec4758d6fd89b60d88669f74f30cdb6bb
https://github.com/qemu/qemu/commit/1a7a31aec4758d6fd89b60d88669f74f30cdb6bb
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Migrate ail-mode-3 spapr cap
This cap did not add the migration code when it was introduced. This
results in migration failure when changing the default using the
command line.
Cc: [email protected]
Fixes: ccc5a4c5e10 ("spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for
H_SET_MODE hcall")
Reviewed-by: Harsh Prateek Bora <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 8af863f2bd976b937f7e3d38b2ab1813b2fa1d9d
https://github.com/qemu/qemu/commit/8af863f2bd976b937f7e3d38b2ab1813b2fa1d9d
Author: Akihiko Odaki <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/spapr_vof.c
Log Message:
-----------
spapr: Free stdout path
This fixes LeakSanitizer warnings.
Signed-off-by: Akihiko Odaki <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 785c8637f9d2362a8addf4ded853d975955a9d6b
https://github.com/qemu/qemu/commit/785c8637f9d2362a8addf4ded853d975955a9d6b
Author: Akihiko Odaki <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/vof.c
Log Message:
-----------
ppc/vof: Fix unaligned FDT property access
FDT properties are aligned by 4 bytes, not 8 bytes.
Signed-off-by: Akihiko Odaki <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c6a3d7bc9e3acf2431ac23ae6dbeb28aa92f873c
https://github.com/qemu/qemu/commit/c6a3d7bc9e3acf2431ac23ae6dbeb28aa92f873c
Author: Harsh Prateek Bora <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M accel/kvm/kvm-all.c
M include/sysemu/kvm.h
Log Message:
-----------
accel/kvm: Introduce kvm_create_and_park_vcpu() helper
There are distinct helpers for creating and parking a KVM vCPU.
However, there can be cases where a platform needs to create and
immediately park the vCPU during early stages of vcpu init which
can later be reused when vcpu thread gets initialized. This would
help detect failures with kvm_create_vcpu at an early stage.
Suggested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 18530e7c57dec3d82d02ed17038661e2005162c1
https://github.com/qemu/qemu/commit/18530e7c57dec3d82d02ed17038661e2005162c1
Author: Harsh Prateek Bora <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M cpu-common.c
M include/exec/cpu-common.h
Log Message:
-----------
cpu-common.c: export cpu_get_free_index to be reused later
This helper provides an easy way to identify the next available free cpu
index which can be used for vcpu creation. Until now, this is being
called at a very later stage and there is a need to be able to call it
earlier (for now, with ppc64) hence the need to export.
Suggested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: cfb52d07f53aa916003d43f69c945c2b42bc6374
https://github.com/qemu/qemu/commit/cfb52d07f53aa916003d43f69c945c2b42bc6374
Author: Harsh Prateek Bora <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: handle vcpu hotplug failure gracefully
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
leading to termination of guest since errp is set to &error_fatal while
calling kvm_init_vcpu. This unexpected behaviour can be avoided by
pre-creating and parking vcpu on success or return error otherwise.
This enables graceful error delivery for any vcpu hotplug failures while
the guest can keep running.
Also introducing KVM AccelCPUClass to init cpu_target_realize for kvm.
Tested OK by repeatedly doing a hotplug/unplug of vcpus as below:
#virsh setvcpus hotplug 40
#virsh setvcpus hotplug 70
error: internal error: unable to execute QEMU command 'device_add':
kvmppc_cpu_realize: vcpu hotplug failed with -12
Signed-off by: Harsh Prateek Bora <[email protected]>
Reported-by: Anushree Mathur <[email protected]>
Suggested-by: Shivaprasad G Bhat <[email protected]>
Suggested-by: Vaibhav Jain <[email protected]>
Tested-by: Anushree Mathur <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 2587a57dbb50257f296b5f28b889e54d0b64c394
https://github.com/qemu/qemu/commit/2587a57dbb50257f296b5f28b889e54d0b64c394
Author: Omar Sandoval <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/arch_dump.c
Log Message:
-----------
target/ppc/arch_dump: set prstatus pid to cpuid
Every other architecture does this, and debuggers need it to be able to
identify which prstatus note corresponds to which CPU.
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Omar Sandoval <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: b9c0a2e01c0f38bdc4ba8f69cf298eeebfb3738b
https://github.com/qemu/qemu/commit/b9c0a2e01c0f38bdc4ba8f69cf298eeebfb3738b
Author: Shivaprasad G Bhat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M linux-headers/asm-powerpc/kvm.h
Log Message:
-----------
linux-header: PPC: KVM: Update one-reg ids for DEXCR, HASHKEYR and HASHPKEYR
This is a placeholder change for these SPRs until the full linux
header update.
Signed-off-by: Shivaprasad G Bhat <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: ca85beb4b783064781a3295feaa7b1a8645f2df9
https://github.com/qemu/qemu/commit/ca85beb4b783064781a3295feaa7b1a8645f2df9
Author: Shivaprasad G Bhat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc/cpu_init: Synchronize DEXCR with KVM for migration
The patch enables DEXCR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_DEXCR.
Signed-off-by: Shivaprasad G Bhat <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 843b243f8620a92f5ff652550b61fc724e5d520c
https://github.com/qemu/qemu/commit/843b243f8620a92f5ff652550b61fc724e5d520c
Author: Shivaprasad G Bhat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc/cpu_init: Synchronize HASHKEYR with KVM for migration
The patch enables HASHKEYR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_HASHKEYR.
Signed-off-by: Shivaprasad G Bhat <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c0840b46d4c8483a93370434f9ea10b8a7b50bde
https://github.com/qemu/qemu/commit/c0840b46d4c8483a93370434f9ea10b8a7b50bde
Author: Shivaprasad G Bhat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc/cpu_init: Synchronize HASHPKEYR with KVM for migration
The patch enables HASHPKEYR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_HASHPKEYR.
Signed-off-by: Shivaprasad G Bhat <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 977e789c4a8ed813d4ab03f17ea20a575bf20cd1
https://github.com/qemu/qemu/commit/977e789c4a8ed813d4ab03f17ea20a575bf20cd1
Author: Aditya Gupta <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M tests/qtest/pnv-xscom.h
Log Message:
-----------
ppc/pnv: Update Power10's cfam id to use Power10 DD2
Power10 DD1.0 was dropped in:
commit 8f054d9ee825 ("ppc: Drop support for POWER9 and POWER10 DD1 chips")
Use the newer Power10 DD2 chips cfam id.
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c6e07f03f7270799a26eb79e17ac40078ad94e5c
https://github.com/qemu/qemu/commit/c6e07f03f7270799a26eb79e17ac40078ad94e5c
Author: Glenn Miles <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: Fix loss of LPC SERIRQ interrupts
The LPC HC irq status register bits are set when an LPC IRQSER input is
asserted. These irq status bits drive the PSI irq to the CPU interrupt
controller. The LPC HC irq status bits are cleared by software writing
to the register with 1's for the bits to clear.
Existing register write was clearing the irq status bits even when the
input was asserted, this results in interrupts being lost.
This fix changes the behavior to keep track of the device IRQ status
in internal state that is separate from the irq status register, and
only allowing the irq status bits to be cleared if the associated
input is not asserted.
Signed-off-by: Glenn Miles <[email protected]>
[np: rebased before P9 PSI SERIRQ patch, adjust changelog/comments]
Reviewed-by: Glenn Miles <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 24c3caff995584342101a181af2eacd67129e5ec
https://github.com/qemu/qemu/commit/24c3caff995584342101a181af2eacd67129e5ec
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function
The POWER8 LPC ISA device irqs all get combined and reported to the line
connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
host controller irqs use that line, and the device irqs get routed to
4 new lines connected to PSI SERIRQ0-3.
POWER9 also introduced a new feature that automatically clears the irq
status in the LPC host controller when EOI'ed, so software does not have
to.
The powernv OPAL (skiboot) firmware managed to work because the LPCHC
irq handler scanned all LPC irqs and handled those including clearing
status even on POWER9 systems. So LPC irqs worked despite OPAL thinking
it was running in POWER9 mode. After this change, UART interrupts show
up on serirq1 which is where OPAL routes them to:
cat /proc/interrupts
...
20: 0 XIVE-IRQ 1048563 Level opal-psi#0:lpchc
...
25: 34 XIVE-IRQ 1048568 Level opal-psi#0:lpc_serirq_mux1
Whereas they previously turn up on lpchc.
Reviewed-by: Glenn Miles <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 53f18b3ef2c3e898e7dae21a1f33f9e2f3eed764
https://github.com/qemu/qemu/commit/53f18b3ef2c3e898e7dae21a1f33f9e2f3eed764
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_adu.c
M hw/ppc/pnv_xscom.c
M hw/ppc/trace-events
A include/hw/ppc/pnv_adu.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO
and PIB. However it also includes control and status registers and other
functions that are exposed as PIB (xscom) registers.
To keep things simple, pnv_xscom.c remains the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 24bd283bccb334109f112839ab6867f0192045d6
https://github.com/qemu/qemu/commit/24bd283bccb334109f112839ab6867f0192045d6
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_adu.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_adu.h
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: Implement ADU access to LPC space
One of the functions of the ADU is indirect memory access engines that
send and receive data via ADU registers.
This implements the ADU LPC memory access functionality sufficiently
for IBM proprietary firmware to access the UART and print characters
to the serial port as it does on real hardware.
This requires a linkage between adu and lpc, which allows adu to
perform memory access in the lpc space.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 7f516cdeef6d62e78ee769855dff95666e6b8c1d
https://github.com/qemu/qemu/commit/7f516cdeef6d62e78ee769855dff95666e6b8c1d
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix msgsnd for POWER8
POWER8 (ISA v2.07S) introduced the doorbell facility, the msgsnd
instruction behaved mostly like msgsndp, it was addressed by TIR
and could only send interrupts between threads on the core.
ISA v3.0 changed msgsnd to be addressed by PIR and can interrupt
any thread in the system.
msgsnd only implements the v3.0 semantics, which can make
multi-threaded POWER8 hang when booting Linux (due to IPIs
failing). This change adds v2.07 semantics.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 060e61436794d13ede9a1d0eb2b1d0cf3b7cfcfd
https://github.com/qemu/qemu/commit/060e61436794d13ede9a1d0eb2b1d0cf3b7cfcfd
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: Add pointer from PnvCPUState to PnvCore
This helps move core state from CPU to core structures.
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 0ca94b2f11223d41258e6a7a046e5ccde831de46
https://github.com/qemu/qemu/commit/0ca94b2f11223d41258e6a7a046e5ccde831de46
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_chiptod.c
M include/hw/ppc/pnv_core.h
M target/ppc/cpu.h
M target/ppc/timebase_helper.c
Log Message:
-----------
ppc/pnv: Move timebase state into PnvCore
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the timebase
side of the state machine to thread 0 of a core.
Move the state out into PnvCore and share it among all threads.
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 60d30cff8472c0bf05a40b0f55221fb4efb768e2
https://github.com/qemu/qemu/commit/60d30cff8472c0bf05a40b0f55221fb4efb768e2
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M include/hw/ppc/pnv_core.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/misc_helper.c
Log Message:
-----------
target/ppc: Move SPR indirect registers into PnvCore
SPRC/SPRD were recently added to all BookS CPUs supported, but
they are only tested on POWER9 and POWER10, so restrict them to
those CPUs.
SPR indirect scratch registers presently replicated per-CPU like
SMT SPRs, but the PnvCore is a better place for them since they
are restricted to P9/P10.
Also add SPR indirect read access to core thread state for POWER9
since skiboot accesses that when booting to check for big-core
mode.
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: d76cb5a53b04d52db1500e83bd6bdfbfeca44e4d
https://github.com/qemu/qemu/commit/d76cb5a53b04d52db1500e83bd6bdfbfeca44e4d
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: use class attribute to limit SMT threads for different machines
Use a class attribute to specify the number of SMT threads per core
permitted for different machines, 8 for powernv8 and 4 for powernv9/10.
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 25de28220cedadac15021ec40047785f30e153fe
https://github.com/qemu/qemu/commit/25de28220cedadac15021ec40047785f30e153fe
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
ppc/pnv: Extend chip_pir class method to TIR as well
The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated topology
of cores and threads.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: feb37fdc821242d86c30bff33abd31bcce01e9e2
https://github.com/qemu/qemu/commit/feb37fdc821242d86c30bff33abd31bcce01e9e2
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_core.c
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
Log Message:
-----------
ppc: Add a core_index to CPUPPCState for SMT vCPUs
The way SMT thread siblings are matched is clunky, using hard-coded
logic that checks the PIR SPR.
Change that to use a new core_index variable in the CPUPPCState,
where all siblings have the same core_index. CPU realize routines have
flexibility in setting core/sibling topology.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 50d8cfb949066e4466700e814a0e26719d70a951
https://github.com/qemu/qemu/commit/50d8cfb949066e4466700e814a0e26719d70a951
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/misc_helper.c
M target/ppc/timebase_helper.c
Log Message:
-----------
target/ppc: Add helpers to check for SMT sibling threads
Add helpers for TCG code to determine if there are SMT siblings
sharing per-core and per-lpar registers. This simplifies the
callers and makes SMT register topology simpler to modify with
later changes.
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 59c921f2297d6e293fde593432acf90d819e4d51
https://github.com/qemu/qemu/commit/59c921f2297d6e293fde593432acf90d819e4d51
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_core.c
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
Log Message:
-----------
ppc: Add has_smt_siblings property to CPUPPCState
The decision to branch out to a slower SMT path in instruction
emulation will become a bit more complicated with the way that
"big-core" topology that will be implemented in subsequent changes.
Hide these details from the wider CPU emulation code with a bool
has_smt_siblings flag that can be set by machine initialisation.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c26504afd5f5cca1addfab5222621bc32a28522f
https://github.com/qemu/qemu/commit/c26504afd5f5cca1addfab5222621bc32a28522f
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: Add a big-core mode that joins two regular cores
POWER9 and POWER10 machines come in two variants, big-core and
small-core. Big-core machines are SMT8 from software's point of view,
but the low level platform topology ("xscom registers and pervasive
addressing"), these look more like a pair of small cores ganged
together.
Presently the way this is modelled is to create one SMT8 PnvCore and add
special cases to xscom and pervasive for big-core mode that tries to
split this into two small cores, but this is becoming too complicated to
manage.
A better approach is to create 2 core structures and ganging them
together to look like an SMT8 core in TCG. Then the xscom and pervasive
models mostly do not need to differentiate big and small core modes.
This change adds initial mode bits and QEMU topology handling to
split SMT8 cores into 2xSMT4 cores.
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: cf0eb929e59cb9074db7b197bb6782a2a47dddda
https://github.com/qemu/qemu/commit/cf0eb929e59cb9074db7b197bb6782a2a47dddda
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Add allow for big-core differences in DT generation
device-tree building needs to account for big-core mode, because it is
driven by qemu cores (small cores). Every second core should be skipped,
and every core should describe threads for both small-cores that make
up the big core.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 27f61d1b0b708b4659894cd0677f65ebed6eaa0b
https://github.com/qemu/qemu/commit/27f61d1b0b708b4659894cd0677f65ebed6eaa0b
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Implement big-core PVR for Power9/10
Power9/10 CPUs have PVR[51] set in small-core mode and clear in big-core
mode. This is used by skiboot firmware.
PVR is not hypervisor-privileged but it is not so important that spapr
to implement this because it's generally masked out of PVR matching code
in kernels, and only used by firmware.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 16ffcb3401ddb991ec746de05595ba62eae45a1b
https://github.com/qemu/qemu/commit/16ffcb3401ddb991ec746de05595ba62eae45a1b
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/misc_helper.c
Log Message:
-----------
ppc/pnv: Implement Power9 CPU core thread state indirect register
Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 78be3218940c0902d165f42ad0cdcd38e66c5df2
https://github.com/qemu/qemu/commit/78be3218940c0902d165f42ad0cdcd38e66c5df2
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_core.h
M target/ppc/timebase_helper.c
Log Message:
-----------
ppc/pnv: Add POWER10 ChipTOD quirk for big-core
POWER10 has a quirk in its ChipTOD addressing that requires the even
small-core to be selected even when programming the odd small-core.
This allows skiboot chiptod init to run in big-core mode.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: b1beb69231c8a6a04ec365614e67729ea9af7cbf
https://github.com/qemu/qemu/commit/b1beb69231c8a6a04ec365614e67729ea9af7cbf
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Add big-core machine property
Big-core implementation is complete, so expose it as a machine
property that may be set with big-core=on option on powernv9 and
powernv10 machines.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: ca4f47752a14221a26cd2bf4710bb21ad2811a22
https://github.com/qemu/qemu/commit/ca4f47752a14221a26cd2bf4710bb21ad2811a22
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Add a CPU nmi and resume function
Power CPUs have an execution control facility that can pause, resume,
and cause NMIs, among other things. Add a function that will nmi a CPU
and resume it if it was paused, in preparation for implementing the
control facility.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c8891955086b2fa795efb7fa0e409e32f25e5447
https://github.com/qemu/qemu/commit/c8891955086b2fa795efb7fa0e409e32f25e5447
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: Implement POWER10 PC xscom registers for direct controls
The PC unit in the processor core contains xscom registers that provide
low level status and control of the CPU.
This implements "direct controls", sufficient for skiboot firmware,
which uses it to send NMI IPIs between CPUs.
POWER10 is sufficiently different from POWER9 (particularly with respect
to QME and special wakeup) that it is not trivial to implement POWER9
support by reusing the code.
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 3b5ea01e98a5e26c1adb13d966f334cb58680cf8
https://github.com/qemu/qemu/commit/3b5ea01e98a5e26c1adb13d966f334cb58680cf8
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_core.h
M target/ppc/cpu_init.c
Log Message:
-----------
ppc/pnv: Add an LPAR per core machine option
Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread"
modes. In per-core mode, some SPRs and IPI doorbells are shared between
threads in a core. In per-thread mode, supervisor and user state is
not shared between threads.
OpenPOWER systems after POWER8 use LPAR per thread mode, and it is
required for KVM. Enterprise systems use LPAR per core mode, as they
partition the machine by core.
Implement a lpar-per-core machine option for powernv machines. This
is fixed true for POWER8 machines, and defaults off for P9 and P10.
With this change, powernv8 SMT now works sufficiently to run Linux,
with a single socket. Multi-threaded KVM guests still have problems,
as does multi-socket Linux boot.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 117664a1e70e6adff1e4384702a9d8343597b5b9
https://github.com/qemu/qemu/commit/117664a1e70e6adff1e4384702a9d8343597b5b9
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Remove ppc target dependency from pnv_xscom.h
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 29318db133d0b2523bda771f76aa50c08842527f
https://github.com/qemu/qemu/commit/29318db133d0b2523bda771f76aa50c08842527f
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/Kconfig
M hw/ssi/Kconfig
M hw/ssi/meson.build
A hw/ssi/pnv_spi.c
M hw/ssi/trace-events
M include/hw/ppc/pnv_xscom.h
A include/hw/ssi/pnv_spi.h
A include/hw/ssi/pnv_spi_regs.h
Log Message:
-----------
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
[np: Fix FDT macro compile for qtest]
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: b4cb930e40f172e2b28a9fbe0189e97469aad648
https://github.com/qemu/qemu/commit/b4cb930e40f172e2b28a9fbe0189e97469aad648
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ssi/pnv_spi.c
M hw/ssi/trace-events
M include/hw/ssi/pnv_spi.h
M include/hw/ssi/pnv_spi_regs.h
Log Message:
-----------
hw/ssi: Extend SPI model
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to the
control by the sequencer and according to the setup defined in the
configuration registers. Sequencer implements the main control logic and
FSM to handle data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 8d970f4162b8a388eef08ee37dab47a650e390ab
https://github.com/qemu/qemu/commit/8d970f4162b8a388eef08ee37dab47a650e390ab
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw/block: Add Microchip's 25CSM04 to m25p80
Add Microchip's 25CSM04 Serial EEPROM to m25p80. 25CSM04 provides 4 Mbits
of Serial EEPROM utilizing the Serial Peripheral Interface (SPI) compatible
bus. The device is organized as 524288 bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: bb44dc48628e9168f16c460f778bbef7a91d7708
https://github.com/qemu/qemu/commit/bb44dc48628e9168f16c460f778bbef7a91d7708
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ssi/pnv_spi.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
hw/ppc: SPI controller wiring to P10 chip
In this commit, create SPI controller on p10 chip and connect cs irq.
The QOM tree of pnv-spi and seeprom are.
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/pib_spic[2] (pnv-spi)
/pnv-spi-bus.2 (SSI)
/xscom-spi[0] (memory-region)
/machine (powernv10-machine)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 533074918727c5fafb11a033fcccaac11ee0227b
https://github.com/qemu/qemu/commit/533074918727c5fafb11a033fcccaac11ee0227b
Author: Chalapathi V <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/pnv-spi-seeprom-test.c
Log Message:
-----------
tests/qtest: Add pnv-spi-seeprom qtest
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V <[email protected]>
Acked-by: Cédric Le Goater <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 8c01b2e1f7e34e6444abb59a544a52192393e798
https://github.com/qemu/qemu/commit/8c01b2e1f7e34e6444abb59a544a52192393e798
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
Log Message:
-----------
pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support
XIVE offers a 'cache watch facility', which allows software to read/update
a potentially cached table entry with no software lock. There's one such
facility in the Virtualization Controller (VC) to update the ESB and END
entries and one in the Presentation Controller (PC) to update the
NVP/NVG/NVC entries.
Each facility has 4 cache watch engines to control the updates and
firmware can request an available engine by querying the hardware
'watch_assign' register of the VC or PC. The engine is then reserved and
is released after the data is updated by reading the 'watch_spec' register
(which also allows to check for a conflict during the update).
If no engine is available, the special value 0xFF is returned and
firmware is expected to repeat the request until an engine becomes
available.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 64770efd668e61128f30d6d50861c7a85ba12ec5
https://github.com/qemu/qemu/commit/64770efd668e61128f30d6d50861c7a85ba12ec5
Author: Michael Kowal <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Structure/define alignment changes
Made changes to some structure and define elements to ease review in
next patchset.
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 76125c0132f27f0b4ba1b71d19027aba1fe62fd9
https://github.com/qemu/qemu/commit/76125c0132f27f0b4ba1b71d19027aba1fe62fd9
Author: Nicholas Piggin <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
pnv/xive: Support cache flush and queue sync inject with notifications
Adds support for writing a completion notification byte in memory
whenever a cache flush or queue sync inject operation is requested by
software. QEMU does not cache any of the XIVE data that is in memory and
therefore it simply writes the completion notification byte at the time
that the operation is requested.
Co-authored-by: Glenn Miles <[email protected]>
Signed-off-by: Glenn Miles <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: d6d5f5c0347b124319ff9c0a43358bdae1d7ea26
https://github.com/qemu/qemu/commit/d6d5f5c0347b124319ff9c0a43358bdae1d7ea26
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Add NVG and NVC to cache watch facility
The cache watch facility uses the same register interface to handle
entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX
specification' register tells the table type. So far, that bit-field
was not read and the code assumed a read/write to the NVP table.
This patch allows to read/write entries in the NVG and NVC table as
well.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 1775b7d1091452dab24ef23ddc1b7c1943a5e9e4
https://github.com/qemu/qemu/commit/1775b7d1091452dab24ef23ddc1b7c1943a5e9e4
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Configure Virtualization Structure Tables through the PC
Both the virtualization layer (VC) and presentation layer (PC) need to
be configured to access the VSTs. Since the information is redundant,
the xive model combines both into one set of tables and only the
definitions going through the VC are kept. The definitions through the
PC are ignored. That works well as long as firmware calls the VC for
all the tables.
For the NVG and NVC tables, it can make sense to only configure them
with the PC, since they are only used by the presenter. So this patch
allows firmware to configure the VST tables through the PC as well.
The definitions are still shared, since the VST tables can be set
through both the VC and/or PC, they are dynamically re-mapped in
memory by first deleting the memory subregion.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 9d7188a2ba6e520934691612915afb98c10823c5
https://github.com/qemu/qemu/commit/9d7188a2ba6e520934691612915afb98c10823c5
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
Log Message:
-----------
pnv/xive2: Enable VST NVG and NVC index compression
Enable NVG and NVC VST tables for index compression which indicates the number
of bits the address is shifted to the right for the table accesses.
The compression values are defined as:
0000 - No compression
0001 - 1 bit shift
0010 - 2 bit shift
....
1000 - 8 bit shift
1001-1111 - No compression
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 4c81813e25d24ece49141572ad5f07d8efe7bf4d
https://github.com/qemu/qemu/commit/4c81813e25d24ece49141572ad5f07d8efe7bf4d
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Set Translation Table for the NVC port space
Set Translation Table for the NVC port space is missing. The xive model
doesn't take into account the remapping of IO operations via the Set
Translation Table but firmware is allowed to define it for the Notify
Virtual Crowd (NVC), like it's already done for the other VST tables.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: fa414eb6655228e274811ade0c7bcddb88acaee5
https://github.com/qemu/qemu/commit/fa414eb6655228e274811ade0c7bcddb88acaee5
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Fail VST entry address computation if table has no VSD
Fail VST entry address computation if firmware doesn't define a descriptor
for one of the Virtualization Structure Tables (VST), there's no point in
trying to compute the address of its entry. Abort the operation and log
an error.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 96c674bf08365ae0ffa2b960a12718bf2ca90079
https://github.com/qemu/qemu/commit/96c674bf08365ae0ffa2b960a12718bf2ca90079
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c
Moving xive2_nvp_pic_print_info() to align with the other "pic_print_info"
functions.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 6adb007357752ff665fde7dd43e5e0afabe7dcbc
https://github.com/qemu/qemu/commit/6adb007357752ff665fde7dd43e5e0afabe7dcbc
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
pnv/xive2: Refine TIMA 'info pic' output
In XIVE Gen 2 there were some minor changes to the TIMA header that were
updated when printed.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 5fc9c71724559be273ee1b68c65ffe45e1386e3c
https://github.com/qemu/qemu/commit/5fc9c71724559be273ee1b68c65ffe45e1386e3c
Author: Frederic Barrat <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
pnv/xive2: Dump more END state with 'info pic'
Additional END state 'info pic' information as added. The 'ignore',
'crowd' and 'precluded escalation control' bits of an Event Notification
Descriptor are all used when delivering an interrupt targeting a VP-group
or crowd.
Signed-off-by: Frederic Barrat <[email protected]>
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: a7e10fab78d91d7d0dee60ce1e4d1b28365d570f
https://github.com/qemu/qemu/commit/a7e10fab78d91d7d0dee60ce1e4d1b28365d570f
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VMX integer add/sub saturate insns to decodetree.
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 8fc7b63adaa860c81119f6f8cd6cc981504bfb7b
https://github.com/qemu/qemu/commit/8fc7b63adaa860c81119f6f8cd6cc981504bfb7b
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Improve VMX integer add/sub saturate instructions.
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 48eda6abfd7ebf3a21c699d8b13d7506b877d1b7
https://github.com/qemu/qemu/commit/48eda6abfd7ebf3a21c699d8b13d7506b877d1b7
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Move ISA300 flag check out of do_helper_XX3.
Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 638f6d553af70ae5a7dc26200d35e385d649ff75
https://github.com/qemu/qemu/commit/638f6d553af70ae5a7dc26200d35e385d649ff75
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move VSX arithmetic and max/min insns to decodetree.
Moving the following instructions to decodetree specification:
x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form
The changes were verfied by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: c1167a9257a22433a16e223a1209c9c72836edee
https://github.com/qemu/qemu/commit/c1167a9257a22433a16e223a1209c9c72836edee
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move VSX logical instructions to decodetree.
Moving the following instructions to decodetree specification :
xxl{and, andc, or, orc, nor, xor, nand, eqv} : XX3-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: cff278c9fa4ed6a8c2e5d2aba6c490e6252a6825
https://github.com/qemu/qemu/commit/cff278c9fa4ed6a8c2e5d2aba6c490e6252a6825
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Moving VSX scalar storage access insns to decodetree.
Moving the following instructions to decodetree specification :
lxs{d, iwa, ibz, ihz, iwz, sp}x : X-form
stxs{d, ib, ih, iw, sp}x : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 29df8d950e20f5caeec137fa20bc1245fb9f702e
https://github.com/qemu/qemu/commit/29df8d950e20f5caeec137fa20bc1245fb9f702e
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/mem_helper.c
M target/ppc/translate.c
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move VSX vector with length storage access insns to decodetree.
Moving the following instructions to decodetree specification :
{l, st}xvl(l) : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also added a new function do_ea_calc_ra to calculate the effective address :
EA <- (RA == 0) ? 0 : GPR[RA], which is now used by the above-said insns,
and shall be used later by (p){lx, stx}vp insns.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
[np: Fix 32-bit build]
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 7419dc5b2b5bcc929d91e8920692041a8f6d1977
https://github.com/qemu/qemu/commit/7419dc5b2b5bcc929d91e8920692041a8f6d1977
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move VSX vector storage access insns to decodetree.
Moving the following instructions to decodetree specification:
lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: e77d736d2a069d462b686f2207df06859abb9ace
https://github.com/qemu/qemu/commit/e77d736d2a069d462b686f2207df06859abb9ace
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move VSX fp compare insns to decodetree.
Moving the following instructions to decodetree specification:
xvcmp{eq, gt, ge, ne}{s, d}p : XX3-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: bf15bf0a1d07913f22e9e82a0b829d45efc69195
https://github.com/qemu/qemu/commit/bf15bf0a1d07913f22e9e82a0b829d45efc69195
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: acbdee4588d972b8553b2c5c9ec4c17c2fe399a7
https://github.com/qemu/qemu/commit/acbdee4588d972b8553b2c5c9ec4c17c2fe399a7
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Update VMX storage access insns to use tcg_gen_qemu_ld/st_i128.
Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.
Reviewed-by: Richard Henderson <[email protected]>
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 625b58fde83d226c6ea61004edad04858481c0e4
https://github.com/qemu/qemu/commit/625b58fde83d226c6ea61004edad04858481c0e4
Author: Chinmay Rath <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128.
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Reviewed-by: Richard Henderson <[email protected]>
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 698faf3304805d8951bb0de0ab08f5d2dbeae7cf
https://github.com/qemu/qemu/commit/698faf3304805d8951bb0de0ab08f5d2dbeae7cf
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Reorganise and rename ppc_hash32_pp_prot()
Reorganise ppc_hash32_pp_prot() swapping the if legs so it does not
test for negative first and clean up to make it shorter. Also rename
it to ppc_hash32_prot().
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 5a902297eedfcef267e525df1e0cf64d95a7d885
https://github.com/qemu/qemu/commit/5a902297eedfcef267e525df1e0cf64d95a7d885
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove local name for a constant
The mmask local variable is a less descriptive local name for a
constant. Drop it and use the constant directly in the two places it
is needed.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 15465dd8b9e29d2c18d5eecfa0ba0fbdc6c8e511
https://github.com/qemu/qemu/commit/15465dd8b9e29d2c18d5eecfa0ba0fbdc6c8e511
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove single use local variable
The ptem variable in ppc6xx_tlb_pte_check() is used only once,
simplify by removing it as the value is already clear itself without
adding a local name for it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: f6b50257c7c7297be6bcafe8ff977a38c965d0c0
https://github.com/qemu/qemu/commit/f6b50257c7c7297be6bcafe8ff977a38c965d0c0
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove single use local variable
The ptev variable in ppc6xx_tlb_pte_check() is used only once and just
obfuscates an otherwise clear value. Get rid of it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 3208c36ad34213eee36b1427d8cb944cfa0a192c
https://github.com/qemu/qemu/commit/3208c36ad34213eee36b1427d8cb944cfa0a192c
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove another single use local variable
In ppc6xx_tlb_pte_check() the pteh variable is used only once to
compare to the h parameter of the function. Inline its value and use
pteh name for the function parameter which is more descriptive.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 7ee01cf8632e0666f933a88ddd97315cc17cc4e0
https://github.com/qemu/qemu/commit/7ee01cf8632e0666f933a88ddd97315cc17cc4e0
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove yet another single use local variable
In ppc6xx_tlb_pte_check() the pp variable is used only once to pass it
to a function parameter with the same name. Remove the local and
inline the value. Also use named constant for the hex value to make it
clearer.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 0e65cea1bd33d4f2917b272c3b03e0eeb8e7b6fd
https://github.com/qemu/qemu/commit/0e65cea1bd33d4f2917b272c3b03e0eeb8e7b6fd
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Return directly in ppc6xx_tlb_pte_check()
Instead of using a local ret variable return directly and remove the
local.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 9e2d6802b5c7d15d0d82bb7c9370ebd3df7492ac
https://github.com/qemu/qemu/commit/9e2d6802b5c7d15d0d82bb7c9370ebd3df7492ac
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Simplify ppc6xx_tlb_pte_check()
Invert conditions to avoid deep nested ifs and return early instead.
Remove some obvious comments that don't add more clarity.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 0e2d7fc817678d8eedd8cae33bb7c191887466c8
https://github.com/qemu/qemu/commit/0e2d7fc817678d8eedd8cae33bb7c191887466c8
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove unused field from mmu_ctx_t
The eaddr field of mmu_ctx_t is set once but never used so can be
removed.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: f6f8838b055d231ee4bfc31ddaac95fae20834b6
https://github.com/qemu/qemu/commit/f6f8838b055d231ee4bfc31ddaac95fae20834b6
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove hash field from mmu_ctx_t
Return hash value via a parameter and remove it from mmu_ctx.t.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: f8e0cc94192bd040421ff704a8efdc3a83391ffe
https://github.com/qemu/qemu/commit/f8e0cc94192bd040421ff704a8efdc3a83391ffe
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove pte_update_flags()
This function is used only once, its return value is ignored and one
of its parameter is a return value from a previous call. It is better
to inline it in the caller and remove it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 691cf34f216141138bb0289735a762dd7d812137
https://github.com/qemu/qemu/commit/691cf34f216141138bb0289735a762dd7d812137
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove nx field from mmu_ctx_t
Pass it as a parameter instead. Also use named constants instead of
hex values when extracting bits from SR.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: aaf5845b87c6acb7f3e95ea8b45947f98c3fdc7e
https://github.com/qemu/qemu/commit/aaf5845b87c6acb7f3e95ea8b45947f98c3fdc7e
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Convert local variable to bool
In mmu6xx_get_physical_address() ds is used as bool, declare it as
such. Also use named constant instead of hex value.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 8abd6d4288f69627f49d1e6e228d2f0d9d490c21
https://github.com/qemu/qemu/commit/8abd6d4288f69627f49d1e6e228d2f0d9d490c21
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove single use local variable
In mmu6xx_get_physical_address() tagtet_page_bits local is declared
only to use TARGET_PAGE_BITS once. Drop the unneeded variable.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 40df08d2239f00abacdd58a39c34a66264ec91a9
https://github.com/qemu/qemu/commit/40df08d2239f00abacdd58a39c34a66264ec91a9
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Simplify a switch statement
In mmu6xx_get_physical_address() the switch handles all cases so the
default is never reached and can be dropped. Also group together cases
which just return -4.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 0ce61ffaf1c573fdbd2079214499b435b71a1b83
https://github.com/qemu/qemu/commit/0ce61ffaf1c573fdbd2079214499b435b71a1b83
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Inline and remove ppc6xx_tlb_pte_check()
This function is only called once and we can make the caller simpler
by inlining it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: cab21e2ecb917abec597a184fd44d479b4bb1e66
https://github.com/qemu/qemu/commit/cab21e2ecb917abec597a184fd44d479b4bb1e66
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove ptem field from mmu_ctx_t
Instead of passing around ptem in context use it once in the same
function so it can be removed from mmu_ctx_t.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 719a1da19ee67cfd3ef5b50f778d0204daaeb0b2
https://github.com/qemu/qemu/commit/719a1da19ee67cfd3ef5b50f778d0204daaeb0b2
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Add function to get protection key for hash32 MMU
Add a function to get key bit from SR and use it instead of open coded
version.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 620ba617df15ae0bce3be794c870525e329ab78c
https://github.com/qemu/qemu/commit/620ba617df15ae0bce3be794c870525e329ab78c
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
Log Message:
-----------
target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_prot()
This is used only once and can be inlined.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: fa7f2cb91b8f6805ec5d8581ca067ac83acc287e
https://github.com/qemu/qemu/commit/fa7f2cb91b8f6805ec5d8581ca067ac83acc287e
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Init variable in function that relies on it
The ppc6xx_tlb_check() relies on the caller to initialise raddr field
in ctx. Move this init from the only caller into the function.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: da5c1d20e9d63575cb358158895a0efa55682c35
https://github.com/qemu/qemu/commit/da5c1d20e9d63575cb358158895a0efa55682c35
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove key field from mmu_ctx_t
Pass it as a function parameter and remove it from mmu_ctx_t.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: aa781c102a445e1007a307a972fed24c66b9c24c
https://github.com/qemu/qemu/commit/aa781c102a445e1007a307a972fed24c66b9c24c
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Stop using ctx in ppc6xx_tlb_check()
Pass raddr and prot in function parameters instead.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 68bf3a7bbc64d75d6a78a7d31b6b26e343a96320
https://github.com/qemu/qemu/commit/68bf3a7bbc64d75d6a78a7d31b6b26e343a96320
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Rename function parameter
Rename parameter of get_bat_6xx_tlb() from virtual to eaddr to match
other functions.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 6ca35e8763e9c37a9cedd28d286f78fbbf45968c
https://github.com/qemu/qemu/commit/6ca35e8763e9c37a9cedd28d286f78fbbf45968c
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Use defines instead of numeric constants
Replace some BAT related constants with defines from mmu-hash32.h
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: d323338629588ea985c68384642169045ca0e16d
https://github.com/qemu/qemu/commit/d323338629588ea985c68384642169045ca0e16d
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc: Remove bat_size_prot()
There is already a hash32_bat_prot() function that does most if this
and the rest can be inlined. Export hash32_bat_prot() and rename it to
ppc_hash32_bat_prot() to match other functions and use it in
get_bat_6xx_tlb().
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 7e590cf6160ab2d3b626f67312f605b7e410e82d
https://github.com/qemu/qemu/commit/7e590cf6160ab2d3b626f67312f605b7e410e82d
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb()
Pass raddr and prot in function parameters instead
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: bfb5a5eee5cfbe9f248472f7489fed241a2dab21
https://github.com/qemu/qemu/commit/bfb5a5eee5cfbe9f248472f7489fed241a2dab21
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common.c: Remove mmu_ctx_t
Completely get rid of mmu_ctx_t after converting the remaining
functions to pass raddr and prot without the context struct.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 51993bef122896b29d1be218d536b6b3211cf2f1
https://github.com/qemu/qemu/commit/51993bef122896b29d1be218d536b6b3211cf2f1
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
Log Message:
-----------
target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr()
This function is used only once and does not add more clarity than
doing it inline.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 9eb0530033ac3a52fcca055213bc512e4e29b954
https://github.com/qemu/qemu/commit/9eb0530033ac3a52fcca055213bc512e4e29b954
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
Log Message:
-----------
target/ppc/mmu-hash32.c: Move get_pteg_offset32() to the header
This function is a simple shared function, move it to other similar
static inline functions in the header.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 14a43ab3335afb3f68ca103739405178abe070ea
https://github.com/qemu/qemu/commit/14a43ab3335afb3f68ca103739405178abe070ea
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M hw/ppc/spapr_vhyp_mmu.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc: Unexport some functions from mmu-book3s-v3.h
The ppc_hash64_hpt_base() and ppc_hash64_hpt_mask() functions are
mostly used by mmu-hash64.c only but there is one call to
ppc_hash64_hpt_mask() in hw/ppc/spapr_vhyp_mmu.c.in a helper function
that can be moved to mmu-hash64.c which allows these functions to be
removed from the header.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: b864074ce074006f9bcc66a11cd4205355abb9ac
https://github.com/qemu/qemu/commit/b864074ce074006f9bcc66a11cd4205355abb9ac
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
Log Message:
-----------
target/ppc/mmu-radix64: Remove externally unused parts from header
Move the parts not needed outside of mmu-radix64.c from the header to
the C file to leave only parts in the header that need to be exported.
Also drop unneded include of this header.
Signed-off-by: BALATON Zoltan <[email protected]>
Acked-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: d741ecffd2ca260ce7875a4596f17736b5ccb7c3
https://github.com/qemu/qemu/commit/d741ecffd2ca260ce7875a4596f17736b5ccb7c3
Author: BALATON Zoltan <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Remove includes from mmu-book3s-v3.h
Drop includes from header that is not needed by the header itself and
only include them from C files that really need it.
Signed-off-by: BALATON Zoltan <[email protected]>
Acked-by: Nicholas Piggin <[email protected]>
Signed-off-by: Nicholas Piggin <[email protected]>
Commit: 93b799fafd9170da3a79a533ea6f73a18de82e22
https://github.com/qemu/qemu/commit/93b799fafd9170da3a79a533ea6f73a18de82e22
Author: Richard Henderson <[email protected]>
Date: 2024-07-26 (Fri, 26 Jul 2024)
Changed paths:
M accel/kvm/kvm-all.c
M cpu-common.c
M hw/block/m25p80.c
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
M hw/intc/xive.c
M hw/intc/xive2.c
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_adu.c
M hw/ppc/pnv_chiptod.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_xscom.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_vhyp_mmu.c
M hw/ppc/spapr_vof.c
M hw/ppc/trace-events
M hw/ppc/vof.c
M hw/ssi/Kconfig
M hw/ssi/meson.build
A hw/ssi/pnv_spi.c
M hw/ssi/trace-events
M include/exec/cpu-common.h
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_adu.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_lpc.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/spapr.h
M include/hw/ppc/xive2_regs.h
A include/hw/ssi/pnv_spi.h
A include/hw/ssi/pnv_spi_regs.h
M include/sysemu/kvm.h
M linux-headers/asm-powerpc/kvm.h
M target/ppc/arch_dump.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/kvm.c
M target/ppc/mem_helper.c
M target/ppc/misc_helper.c
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_common.c
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
M tests/qtest/meson.build
A tests/qtest/pnv-spi-seeprom-test.c
M tests/qtest/pnv-xscom.h
M tests/tcg/ppc64/Makefile.target
Log Message:
-----------
Merge tag 'pull-ppc-for-9.1-2-20240726-1' of https://gitlab.com/npiggin/qemu
into staging
fixes
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# gpg: Signature made Fri 26 Jul 2024 09:52:27 AM AEST
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.1-2-20240726-1' of https://gitlab.com/npiggin/qemu: (96
commits)
target/ppc: Remove includes from mmu-book3s-v3.h
target/ppc/mmu-radix64: Remove externally unused parts from header
target/ppc: Unexport some functions from mmu-book3s-v3.h
target/ppc/mmu-hash32.c: Move get_pteg_offset32() to the header
target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr()
target/ppc/mmu_common.c: Remove mmu_ctx_t
target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb()
target/ppc: Remove bat_size_prot()
target/ppc/mmu_common.c: Use defines instead of numeric constants
target/ppc/mmu_common.c: Rename function parameter
target/ppc/mmu_common.c: Stop using ctx in ppc6xx_tlb_check()
target/ppc/mmu_common.c: Remove key field from mmu_ctx_t
target/ppc/mmu_common.c: Init variable in function that relies on it
target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_prot()
target/ppc: Add function to get protection key for hash32 MMU
target/ppc/mmu_common.c: Remove ptem field from mmu_ctx_t
target/ppc/mmu_common.c: Inline and remove ppc6xx_tlb_pte_check()
target/ppc/mmu_common.c: Simplify a switch statement
target/ppc/mmu_common.c: Remove single use local variable
target/ppc/mmu_common.c: Convert local variable to bool
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/8e466dd09246...93b799fafd91
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