Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: a5397d805d519f89f35bade33c197cf7e460c9c3
https://github.com/qemu/qemu/commit/a5397d805d519f89f35bade33c197cf7e460c9c3
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/arm/omap1.c
M include/hw/arm/omap.h
Log Message:
-----------
hw/arm/omap1: Remove unused omap_uwire_attach() method
The recently removed 'cheetah' machine was the single user
of the omap_uwire_attach() method. Remove it altogether with
the uWireSlave structure. Replace the send/receive callbacks
by Unimplemented logging.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: d1613f2a5395f52a6537b0117bb219d832213489
https://github.com/qemu/qemu/commit/d1613f2a5395f52a6537b0117bb219d832213489
Author: Román Cárdenas Rodríguez <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32_rcc.c
M hw/misc/trace-events
A include/hw/misc/stm32_rcc.h
Log Message:
-----------
hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs
Generic RCC class for STM32 devices. It can be used for most of
the STM32 chips. Note that it only implements enable and reset
capabilities.
Signed-off-by: Roman Cardenas Rodriguez <[email protected]>
[PMM: tweaked commit message, added MAINTAINERS lines]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 950dff9aa4dc1f287ea001e7d2689dcc76a7f1c4
https://github.com/qemu/qemu/commit/950dff9aa4dc1f287ea001e7d2689dcc76a7f1c4
Author: Román Cárdenas Rodríguez <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/system/arm/stm32.rst
M hw/arm/Kconfig
M hw/arm/stm32f405_soc.c
M include/hw/arm/stm32f405_soc.h
Log Message:
-----------
hw/arm/stm32f405: Add RCC device to stm32f405 SoC
Add the reset and clock controller device to the stm32f405 SoC.
Signed-off-by: Roman Cardenas Rodriguez <[email protected]>
[PMM: tweak commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e0c0ea6eca4f210a52b9742817586cc97b1ee434
https://github.com/qemu/qemu/commit/e0c0ea6eca4f210a52b9742817586cc97b1ee434
Author: Alexandra Diupina <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: [email protected]
Fixes: d2c0c6aab6 ("hw/intc/arm_gicv3: Handle icv_nmiar1_read() for
icc_nmiar1_read()")
Signed-off-by: Alexandra Diupina <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 12dc8f6eca1ead876142fd3d6731cf3da1295f2a
https://github.com/qemu/qemu/commit/12dc8f6eca1ead876142fd3d6731cf3da1295f2a
Author: Alexandra Diupina <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICC_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: [email protected]
Fixes: 28cca59c46 ("hw/intc/arm_gicv3: Add NMI handling CPU interface
registers")
Signed-off-by: Alexandra Diupina <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3db74afec3ca87f81fbdf5918ed1e21d837fbfab
https://github.com/qemu/qemu/commit/3db74afec3ca87f81fbdf5918ed1e21d837fbfab
Author: Alexandra Diupina <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: [email protected]
Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs")
Signed-off-by: Alexandra Diupina <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: b91b8fe79d093543b05db771b1e4a13395d51cfb
https://github.com/qemu/qemu/commit/b91b8fe79d093543b05db771b1e4a13395d51cfb
Author: Inès Varhol <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/arm/stm32l4x5_soc.c
M hw/misc/stm32l4x5_syscfg.c
M include/hw/misc/stm32l4x5_syscfg.h
Log Message:
-----------
hw/misc: Create STM32L4x5 SYSCFG clock
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
corresponding clock from STM32L4x5 RCC.
Signed-off-by: Inès Varhol <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Luc Michel <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9240d65e0e205b2a6df5e304e64451c32995b878
https://github.com/qemu/qemu/commit/9240d65e0e205b2a6df5e304e64451c32995b878
Author: Inès Varhol <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/devel/clocks.rst
M hw/core/clock.c
Log Message:
-----------
hw/clock: Expose 'qtest-clock-period' QOM property for QTests
Expose the clock period via the QOM 'qtest-clock-period' property so it
can be used in QTests. This property is only accessible in QTests (not
via HMP).
Signed-off-by: Inès Varhol <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Luc Michel <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f87e4061fc1c887df8505e658fb1706f18195598
https://github.com/qemu/qemu/commit/f87e4061fc1c887df8505e658fb1706f18195598
Author: Inès Varhol <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
A tests/qtest/stm32l4x5.h
M tests/qtest/stm32l4x5_gpio-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
M tests/qtest/stm32l4x5_usart-test.c
Log Message:
-----------
tests/qtest: Check STM32L4x5 clock connections
For USART, GPIO and SYSCFG devices, check that clock frequency before
and after enabling the peripheral clock in RCC is correct.
Signed-off-by: Inès Varhol <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Luc Michel <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ff346d79f29d27283b2601e5e9b61909edd52df7
https://github.com/qemu/qemu/commit/ff346d79f29d27283b2601e5e9b61909edd52df7
Author: Strahinja Jankovic <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/ssi/Kconfig
A hw/ssi/allwinner-a10-spi.c
M hw/ssi/meson.build
M hw/ssi/trace-events
A include/hw/ssi/allwinner-a10-spi.h
Log Message:
-----------
hw/ssi: Allwinner A10 SPI emulation
This patch implements Allwinner A10 SPI controller emulation.
Only master-mode functionality is implemented.
Since U-Boot and Linux SPI drivers for Allwinner A10 perform only
byte-wide CPU access (no DMA) to the transmit and receive registers of
the peripheral, the emulated controller does not implement DMA control,
and supports only byte-wide access to transmit and receive registers
(half-word and word accesses will be treated as byte accesses).
Signed-off-by: Strahinja Jankovic <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e88a1813e40020a54072041033ee647bf19f241e
https://github.com/qemu/qemu/commit/e88a1813e40020a54072041033ee647bf19f241e
Author: Strahinja Jankovic <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/system/arm/cubieboard.rst
M hw/arm/Kconfig
M hw/arm/allwinner-a10.c
M include/hw/arm/allwinner-a10.h
Log Message:
-----------
hw/arm: Add SPI to Allwinner A10
The Allwinner A10 SPI controller is added to the Allwinner A10
description, so it is available when Cubieboard is emulated.
Update the documentation for Cubieboard to indicate SPI availability.
Signed-off-by: Strahinja Jankovic <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 60aa235be2a7d35e2e4f99cb0c35713c13cd6c9f
https://github.com/qemu/qemu/commit/60aa235be2a7d35e2e4f99cb0c35713c13cd6c9f
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/intc/omap_intc.c
M include/hw/arm/omap.h
Log Message:
-----------
hw/intc/omap_intc: Remove now-unnecessary abstract base class
The OMAP interrupt controller code used to have an omap-intc
class and an omap2-intc class, which shared common code via
the abstract class common-omap-intc. Now we have deleted
omap2-intc, we don't need the separate abstract base class;
fold int into omap-intc.
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 6e08d364c23b78148145a0fb723a03dbd662d298
https://github.com/qemu/qemu/commit/6e08d364c23b78148145a0fb723a03dbd662d298
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: Use correct masks for IBRD and FBRD
In commit b88cfee90268cad we defined masks for the IBRD and FBRD
integer and fractional baud rate divider registers, to prevent the
guest from writing invalid values which could cause division-by-zero.
Unfortunately we got the mask values the wrong way around: the FBRD
register is six bits and the IBRD register is 16 bits, not
vice-versa.
You would only run into this bug if you programmed the UART to a baud
rate of less than 9600, because for 9600 baud and above the IBRD
value will fit into 6 bits, as per the table in
https://developer.arm.com/documentation/ddi0183/g/programmers-model/register-descriptions/fractional-baud-rate-register--uartfbrd
The only visible effects would be that the value read back from
the register by the guest would be truncated, and we would
print an incorrect baud rate in the debug logs.
Cc: [email protected]
Fixes: b88cfee90268 ("hw/char/pl011: Avoid division-by-zero in
pl011_get_baudrate()")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2610
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Gavin Shan <[email protected]>
Message-id: [email protected]
Commit: 544718436fd406a0705e37d00829b7e2925ab1fa
https://github.com/qemu/qemu/commit/544718436fd406a0705e37d00829b7e2925ab1fa
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
R docs/devel/blkdebug.txt
A docs/devel/testing/blkdebug.rst
M docs/devel/testing/index.rst
Log Message:
-----------
docs/devel/blkdebug: Convert to rST format
Convert blkdebug.txt to rST format. We put it into index-build.rst
because it falls under the "test" part of "QEMU Build and Test
System".
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-id: [email protected]
Commit: e81f5d011bc292a16df0118bad168f6b529190b5
https://github.com/qemu/qemu/commit/e81f5d011bc292a16df0118bad168f6b529190b5
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
R docs/devel/blkverify.txt
A docs/devel/testing/blkverify.rst
M docs/devel/testing/index.rst
Log Message:
-----------
docs/devel/blkverify: Convert to rST format
Convert blkverify.txt to rST format.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-id: [email protected]
Commit: ac7fe8a17bb89bfcbc0563ad7ebfd1aea3ba1545
https://github.com/qemu/qemu/commit/ac7fe8a17bb89bfcbc0563ad7ebfd1aea3ba1545
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
M docs/devel/index-api.rst
A docs/devel/lockcnt.rst
R docs/devel/lockcnt.txt
Log Message:
-----------
docs/devel/lockcnt: Convert to rST format
Convert docs/devel/lockcnt.txt to rST format.
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: a684835fc1e38f2dfa5f769bf72e7f84eb3c412b
https://github.com/qemu/qemu/commit/a684835fc1e38f2dfa5f769bf72e7f84eb3c412b
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/devel/index-internals.rst
A docs/devel/multiple-iothreads.rst
R docs/devel/multiple-iothreads.txt
Log Message:
-----------
docs/devel/multiple-iothreads: Convert to rST format
Convert docs/devel/multiple-iothreads.txt to rST format.
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: 4c09f955d75dbe770ba9af952bd8eed896bb4199
https://github.com/qemu/qemu/commit/4c09f955d75dbe770ba9af952bd8eed896bb4199
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
M docs/devel/index-internals.rst
A docs/devel/rcu.rst
R docs/devel/rcu.txt
Log Message:
-----------
docs/devel/rcu: Convert to rST format
Convert docs/devel/rcu.txt to rST format.
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: 640d55eff0ceb1deb6195f5886b7ec79468e3771
https://github.com/qemu/qemu/commit/640d55eff0ceb1deb6195f5886b7ec79468e3771
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
M accel/accel-blocker.c
M docs/devel/lockcnt.rst
M hw/core/cpu-common.c
M include/block/aio.h
M include/hw/core/cpu.h
A include/qemu/lockcnt.h
M include/qemu/thread.h
M util/aio-posix.c
M util/aio-win32.c
M util/async.c
M util/fdmon-epoll.c
M util/lockcnt.c
Log Message:
-----------
include: Move QemuLockCnt APIs to their own header
Currently the QemuLockCnt data structure and associated functions are
in the include/qemu/thread.h header. Move them to their own
qemu/lockcnt.h. The main reason for doing this is that it means we
can autogenerate the documentation comments into the docs/devel
documentation.
The copyright/author in the new header is drawn from lockcnt.c,
since the header changes were added in the same commit as
lockcnt.c; since neither thread.h nor lockcnt.c state an explicit
license, the standard default of GPL-2-or-later applies.
We include the new header (and the .c file, which was accidentally
omitted previously) in the "RCU" part of MAINTAINERS, since that
is where the lockcnt.rst documentation is categorized.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Paolo Bonzini <[email protected]>
Message-id: [email protected]
Commit: 18906b0f57c12c1177e45d3de4a7e4bad7e43115
https://github.com/qemu/qemu/commit/18906b0f57c12c1177e45d3de4a7e4bad7e43115
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/devel/lockcnt.rst
M include/qemu/lockcnt.h
Log Message:
-----------
docs/devel/lockcnt: Include kernel-doc API documentation
Pull in the kernel-doc API documentation into the lockcnt docs.
This requires us to fix one rST markup syntax error in the
header file comments.
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: c5171b26bbb09e15ef619b011570f1641e1686a4
https://github.com/qemu/qemu/commit/c5171b26bbb09e15ef619b011570f1641e1686a4
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/adc/Kconfig
R hw/adc/max111x.c
M hw/adc/meson.build
R include/hw/adc/max111x.h
Log Message:
-----------
hw/adc: Remove MAX111X device
The MAX111X ADC device was used only by the XScale-based
Zaurus machine types. Now they have all been removed, we can
drop this device model too.
Because this device is an SSI device, in theory it could be created
by users on the command line for boards with a different SSI
controller, but we don't believe users are doing this -- it would be
impossible on the command line to connect up the GPIO inputs which
correspond to ADC inputs, or the GPIO output which is an interrupt
line. The only example a web search produces for "device max1111" or
"device max1110" is our own bug report
https://gitlab.com/qemu-project/qemu/-/issues/2228
where it's used as an example of a bogus command that causes an
assertion in an aspeed machine type that wasn't expecting anything
other than flash devices on its SMC bus.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 6b1ffb5b5d43ca1344f7f9c420c225d4c57f8384
https://github.com/qemu/qemu/commit/6b1ffb5b5d43ca1344f7f9c420c225d4c57f8384
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/gpio/Kconfig
R hw/gpio/max7310.c
M hw/gpio/meson.build
Log Message:
-----------
hw/gpio: Remove MAX7310 device
The MAX7310 GPIO controller was used only by the XScale-based Zaurus
machine types. Now they have been removed we can remove this device
model as well.
Because this device is an I2C device, in theory it could be created
by users on the command line for boards with a different I2c
controller, but we don't believe users are doing this -- it would be
impossible on the command line to connect up the GPIO inputs/outputs.
The only example a web search produces for "device max7310" is a user
trying to create this because they didn't realize that there was no
way to manipulate the GPIO lines.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: a435d996e0d8e5164b7424df453bd30bd3163473
https://github.com/qemu/qemu/commit/a435d996e0d8e5164b7424df453bd30bd3163473
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/ide/Kconfig
M hw/ide/meson.build
R hw/ide/microdrive.c
M include/hw/pcmcia.h
Log Message:
-----------
hw/ide: Remove DSCM-1XXXX microdrive device model
The DSCM-1XXXX microdrive device model was used only by the
XScale-based Zaurus machine types. Now they have been removed, we
can delete this device too.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 264f8f09a81d9a8588d1028dedca136f71dd2622
https://github.com/qemu/qemu/commit/264f8f09a81d9a8588d1028dedca136f71dd2622
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/Kconfig
M hw/meson.build
R hw/pcmcia/Kconfig
R hw/pcmcia/meson.build
R hw/pcmcia/pcmcia.c
R include/hw/pcmcia.h
Log Message:
-----------
hw: Remove PCMCIA subsystem
The only PCMCIA subsystem was the PXA2xx SoC and the machines
using it, which have now been removed. Although in theory
we have a few machine types which have PCMCIA (e.g. kzm,
the strongarm machines, sh4's sh7750), none of those machines
implement their PCMCIA controller, and they're all old and
no longer very interesting machine types.
Rather than keeping all the PCMCIA code in-tree without any
active users of it, delete it. If we need PCMCIA in future
we can always resurrect it.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: c8e8ef67cd1bc397da6968daed4bed0731814f86
https://github.com/qemu/qemu/commit/c8e8ef67cd1bc397da6968daed4bed0731814f86
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/arm/Kconfig
M hw/block/Kconfig
R hw/block/ecc.c
M hw/block/meson.build
M hw/misc/Kconfig
M include/hw/block/flash.h
Log Message:
-----------
hw/block: Remove ecc
The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices,
which we have removed, so it is now completely unused.
Note that hw/misc/eccmemctl.c does not in fact use any of the
code frome ecc.c, so that KConfig dependency was incorrect.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: e5144a2a03cbe4936139431b9e4524f748f3c5be
https://github.com/qemu/qemu/commit/e5144a2a03cbe4936139431b9e4524f748f3c5be
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/about/removed-features.rst
M include/sysemu/sysemu.h
M qemu-options.hx
M system/globals.c
M system/vl.c
M ui/input.c
Log Message:
-----------
vl.c: Remove pxa2xx-specific -portrait and -rotate options
The ``-portrait`` and ``-rotate`` options were documented as only
working with the PXA LCD device, and all the machine types using
that display device were removed in 9.2.
These options were intended to simulate a mobile device being
rotated by the user, and had three effects:
* the display output was rotated by 90, 180 or 270 degrees
(implemented in the PXA display device models)
* the mouse/trackpad input was rotated the opposite way
(implemented in generic code)
* the machine model would signal to the guest about its
orientation
(implemented by e.g. the spitz machine model)
Of these three things, the input-rotation was coded without being
restricted to boards which supported the full set of device-rotation
handling, so in theory the options were usable on other machine
models with odd effects (rotating input but not display output). But
this was never intended or documented behaviour, so we can reasonably
drop these command line arguments without a formal deprecate-and-drop
cycle for them.
Remove the options, and their implementation and documentation.
Describe the removal in removed-features.rst.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 96f5b8556953360ca67f8533cb8b53d440038fd7
https://github.com/qemu/qemu/commit/96f5b8556953360ca67f8533cb8b53d440038fd7
Author: Akihiko Odaki <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M include/sysemu/dma.h
Log Message:
-----------
dma: Fix function names in documentation
Ensure the function names match.
Signed-off-by: Akihiko Odaki <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9bb9833fd2ef30c5c7306c6f2a15dcc313305ccc
https://github.com/qemu/qemu/commit/9bb9833fd2ef30c5c7306c6f2a15dcc313305ccc
Author: Chao Liu <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/xilinx_zynq: Add various missing unimplemented devices
Add unimplemented-device blocks to the xilinx_zynq board
corresponding to various devices documented in the TRM
and in the device tree.
See: ug585-Zynq-7000-TRM manual B.3 (Module Summary)
Signed-off-by: Chao Liu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
[PMM: tweaked commit message. Removed the clearing of
the ignore_memory_transaction_failures flag]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 683147034eba8a39a721415a059afcaafb404ce4
https://github.com/qemu/qemu/commit/683147034eba8a39a721415a059afcaafb404ce4
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M MAINTAINERS
M accel/accel-blocker.c
M docs/about/removed-features.rst
R docs/devel/blkdebug.txt
R docs/devel/blkverify.txt
M docs/devel/clocks.rst
M docs/devel/index-api.rst
M docs/devel/index-internals.rst
A docs/devel/lockcnt.rst
R docs/devel/lockcnt.txt
A docs/devel/multiple-iothreads.rst
R docs/devel/multiple-iothreads.txt
A docs/devel/rcu.rst
R docs/devel/rcu.txt
A docs/devel/testing/blkdebug.rst
A docs/devel/testing/blkverify.rst
M docs/devel/testing/index.rst
M docs/system/arm/cubieboard.rst
M docs/system/arm/stm32.rst
M hw/Kconfig
M hw/adc/Kconfig
R hw/adc/max111x.c
M hw/adc/meson.build
M hw/arm/Kconfig
M hw/arm/allwinner-a10.c
M hw/arm/omap1.c
M hw/arm/stm32f405_soc.c
M hw/arm/stm32l4x5_soc.c
M hw/arm/xilinx_zynq.c
M hw/block/Kconfig
R hw/block/ecc.c
M hw/block/meson.build
M hw/char/pl011.c
M hw/core/clock.c
M hw/core/cpu-common.c
M hw/gpio/Kconfig
R hw/gpio/max7310.c
M hw/gpio/meson.build
M hw/ide/Kconfig
M hw/ide/meson.build
R hw/ide/microdrive.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/omap_intc.c
M hw/meson.build
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32_rcc.c
M hw/misc/stm32l4x5_syscfg.c
M hw/misc/trace-events
R hw/pcmcia/Kconfig
R hw/pcmcia/meson.build
R hw/pcmcia/pcmcia.c
M hw/ssi/Kconfig
A hw/ssi/allwinner-a10-spi.c
M hw/ssi/meson.build
M hw/ssi/trace-events
M include/block/aio.h
R include/hw/adc/max111x.h
M include/hw/arm/allwinner-a10.h
M include/hw/arm/omap.h
M include/hw/arm/stm32f405_soc.h
M include/hw/block/flash.h
M include/hw/core/cpu.h
A include/hw/misc/stm32_rcc.h
M include/hw/misc/stm32l4x5_syscfg.h
R include/hw/pcmcia.h
A include/hw/ssi/allwinner-a10-spi.h
A include/qemu/lockcnt.h
M include/qemu/thread.h
M include/sysemu/dma.h
M include/sysemu/sysemu.h
M qemu-options.hx
M system/globals.c
M system/vl.c
A tests/qtest/stm32l4x5.h
M tests/qtest/stm32l4x5_gpio-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
M tests/qtest/stm32l4x5_usart-test.c
M ui/input.c
M util/aio-posix.c
M util/aio-win32.c
M util/async.c
M util/fdmon-epoll.c
M util/lockcnt.c
Log Message:
-----------
Merge tag 'pull-target-arm-20241015' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/omap1: Remove unused omap_uwire_attach() method
* stm32f405: Add RCC device to stm32f405 SoC
* arm/gicv3: add missing casts
* hw/misc: Create STM32L4x5 SYSCFG clock
* hw/arm: Add SPI to Allwinner A10
* hw/intc/omap_intc: Remove now-unnecessary abstract base class
* hw/char/pl011: Use correct masks for IBRD and FBRD
* docs/devel: Convert txt files to rST
* Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only
by now-removed omap/pxa2xx boards)
* vl.c: Remove pxa2xx-specific -portrait and -rotate options
* dma: Fix function names in documentation
* hw/arm/xilinx_zynq: Add various missing unimplemented devices
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmcORccZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vQPD/wI17k4SgH6RA100xFdkQCI
# REWgVrhbtkpOKQvLOG57+qyosI+IbNiFuYSzqUUWbTMmlU9FjXIC/H8LL+24Wopb
# xuiRo6aECiIcdG/oImahhaRBAksjR0qvu3+1lvKZ0v/uRm4yma9u7uyJ+iBtOEl9
# tXMJGGY7qdsp7H/duGp2RCSHu3Zl1X6zcaUOAivLdgihoSKDRZzIdLz0i3IkhYMk
# FRSPvtqrrFaJ1izQx/vA+/mm365Uw+2J+v11fKh+Q1556sjeN8a4f+z6Wxe/DiZI
# OY/76QGT2bSaR58MhzsPubzVBOJx/P/APVLsQ3uUUsuq77la7SiXHvtoEUPmBIU/
# +0l7mjIdpqn+EXpIRmcFFrAqSNGBkpP2bSb7QXeyWm0QFpdOWHzN2D8MX4z8+f3t
# WAcfWF6TQtEsbbZlXKrpRCQ3si3dm7crEC764G4nw1uOSRCQt54c+0XkVHH4pTgT
# mJHLP18rpwDWKHlNypJ1V5Nfmp5Ex8j2y5kHzG6unhRIx64FZsPX04zJ1q5OUSlh
# fgd5V92otQKEWX6rl/z58W+J2VBDzByHu2NGoPzzWr3dUZiRPlWc+r437Np/V2yN
# 64WTlL/q02kluK25/MeY5p0FTa1K8rN9Au8zYAMTZISNMyTuzRQAQkrKCEDatnjy
# osRKVLcncMLjnhvO757Waw==
# =nynr
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 15 Oct 2024 11:36:55 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>"
[ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20241015' of
https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
hw/arm/xilinx_zynq: Add various missing unimplemented devices
dma: Fix function names in documentation
vl.c: Remove pxa2xx-specific -portrait and -rotate options
hw/block: Remove ecc
hw: Remove PCMCIA subsystem
hw/ide: Remove DSCM-1XXXX microdrive device model
hw/gpio: Remove MAX7310 device
hw/adc: Remove MAX111X device
docs/devel/lockcnt: Include kernel-doc API documentation
include: Move QemuLockCnt APIs to their own header
docs/devel/rcu: Convert to rST format
docs/devel/multiple-iothreads: Convert to rST format
docs/devel/lockcnt: Convert to rST format
docs/devel/blkverify: Convert to rST format
docs/devel/blkdebug: Convert to rST format
hw/char/pl011: Use correct masks for IBRD and FBRD
hw/intc/omap_intc: Remove now-unnecessary abstract base class
hw/arm: Add SPI to Allwinner A10
hw/ssi: Allwinner A10 SPI emulation
tests/qtest: Check STM32L4x5 clock connections
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/c155d13167c6...683147034eba
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