Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: edafc90ba481c586d0a649f34dcb8cd1f29c4259
https://github.com/qemu/qemu/commit/edafc90ba481c586d0a649f34dcb8cd1f29c4259
Author: Bibo Mao <[email protected]>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M hw/acpi/generic_event_device.c
M include/hw/acpi/generic_event_device.h
Log Message:
-----------
acpi: ged: Add macro for acpi sleep control register
Macro definition is added for acpi sleep control register, ged emulation
driver can use the macro , also it can be used in FDT table if ged is
exposed with FDT table.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: e1ecdc630d7aaee85cbf22b3b6b3a4da19763521
https://github.com/qemu/qemu/commit/e1ecdc630d7aaee85cbf22b3b6b3a4da19763521
Author: Bibo Mao <[email protected]>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch/virt: Add FDT table support with acpi ged pm register
ACPI ged is used for power management on LoongArch virt platform, in
general it is parsed from acpi table. However if system boot directly from
elf kernel, no UEFI bios is provided and acpi table cannot be used also.
Here acpi ged pm register is exposed with FDT table, it is compatbile
with syscon method in FDT table, only that acpi ged pm register is accessed
with 8-bit mode, rather with 32-bit mode.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Tested-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 4521167f5783eca168d7480adbc634c3654d419d
https://github.com/qemu/qemu/commit/4521167f5783eca168d7480adbc634c3654d419d
Author: Bibo Mao <[email protected]>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M target/loongarch/arch_dump.c
Log Message:
-----------
target/loongarch: Avoid bits shift exceeding width of bool type
Variable env->cf[i] is defined as bool type, it is treated as int type
with shift operation. However the max possible width is 56 for the shift
operation, exceeding the width of int type. And there is existing api
read_fcc() which is converted to u64 type with bitwise shift, it can be
used to dump fp registers into coredump note segment.
Resolves: Coverity CID 1561133
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 25d92888b201d34de6fd12ed8df85eb74ddcde90
https://github.com/qemu/qemu/commit/25d92888b201d34de6fd12ed8df85eb74ddcde90
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: e376c2d87cbbad3483adcd5e827bdd144edb7d2c
https://github.com/qemu/qemu/commit/e376c2d87cbbad3483adcd5e827bdd144edb7d2c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M hw/loongarch/meson.build
Log Message:
-----------
hw/loongarch/fw_cfg: Build in common_ss[]
Nothing in LoongArch fw_cfg.c requires target specific definitions.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 95a16ee753d6da651fce8df876333bf7fcf134d9
https://github.com/qemu/qemu/commit/95a16ee753d6da651fce8df876333bf7fcf134d9
Author: Peter Maydell <[email protected]>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M hw/acpi/generic_event_device.c
M hw/loongarch/meson.build
M hw/loongarch/virt.c
M include/hw/acpi/generic_event_device.h
M include/hw/loongarch/virt.h
M target/loongarch/arch_dump.c
Log Message:
-----------
Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-20241016
# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZw91kQAKCRBAov/yOSY+
# 3+RyA/9vpqCesEBch5mzrazO4MT2IxeN2bstF8mY+EyfEwK7Ocg+esRBsigWw56k
# y6RDyCzHg200GL9TC8bJ/nMiMJjXrahhHRPVs8AADazMzX/Ys7E7ntvUUnqqANh6
# ZX8fzNJMKW6qeUVrCIwCC7E+KjfNu32dcxbXCF4mZsehIumpUQ==
# =uk+a
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 16 Oct 2024 09:13:05 BST
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu:
hw/loongarch/fw_cfg: Build in common_ss[]
hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
target/loongarch: Avoid bits shift exceeding width of bool type
hw/loongarch/virt: Add FDT table support with acpi ged pm register
acpi: ged: Add macro for acpi sleep control register
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/08ae519ab8eb...95a16ee753d6
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