Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: abaabb2e601adfe296a64471746a997eabcc607f
https://github.com/qemu/qemu/commit/abaabb2e601adfe296a64471746a997eabcc607f
Author: Thomas Huth <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M hw/s390x/ipl.c
Log Message:
-----------
hw/s390x/ipl: Provide more memory to the s390-ccw.img firmware
We are going to link the SLOF libc into the s390-ccw.img, and this
libc needs more memory for providing space for malloc() and friends.
Thus bump the memory size that we reserve for the bios to 3 MiB
instead of only 2 MiB. While we're at it, add a proper check that
there is really enough memory assigned to the machine before blindly
using it.
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: a7cfd751fb269de4a93bf1658cb13911c7ac77cc
https://github.com/qemu/qemu/commit/a7cfd751fb269de4a93bf1658cb13911c7ac77cc
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Reset data_gen_ptr correctly
This pointer needs to be reset after overflow just like
code_buf and code_ptr.
Cc: [email protected]
Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools")
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: be46e0bf142d75c1978801d5d2c2394e7dfa304d
https://github.com/qemu/qemu/commit/be46e0bf142d75c1978801d5d2c2394e7dfa304d
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M disas/riscv.c
M disas/riscv.h
Log Message:
-----------
disas/riscv: Fix vsetivli disassembly
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector
instructions")
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f7230e09b1ccfb7055b79dfee981e18d444a118a
https://github.com/qemu/qemu/commit/f7230e09b1ccfb7055b79dfee981e18d444a118a
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M host/include/riscv/host/cpuinfo.h
M util/cpuinfo-riscv.c
Log Message:
-----------
util: Add RISC-V vector extension probe in cpuinfo
Add support for probing RISC-V vector extension availability in
the backend. This information will be used when deciding whether
to use vector instructions in code generation.
Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means
we can convert all of the division into subtraction.
While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X,
we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more
strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in
current QEMU implemenation, the V vector extension depends on the
zve64d extension.
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Tested-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f63e7089b49e0aa031e0247fad7b22b8d650a3fb
https://github.com/qemu/qemu/commit/f63e7089b49e0aa031e0247fad7b22b8d650a3fb
Author: Huang Shiyuan <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M include/tcg/tcg.h
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
A tcg/riscv/tcg-target.opc.h
Log Message:
-----------
tcg/riscv: Add basic support for vector
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other register numbers within the group.
In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the
host runtime needs to adjust LMUL based on the type to use different
register groups.
This presents challenges for TCG's register allocation. Currently, we
avoid modifying the register allocation part of TCG and only expose the
minimum number of vector registers.
For example, when the host vlen is 64 bits and type is TCG_TYPE_V256, with
LMUL equal to 4, we use 4 vector registers as one register group. We can
use a maximum of 8 register groups, but the V0 register number is reserved
as a mask register, so we can effectively use at most 7 register groups.
Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers are
forced to be used. This is because TCG cannot yet dynamically constrain
registers with type; likewise, when the host vlen is 128 bits and
TCG_TYPE_V256, we can use at most 15 registers.
There is not much pressure on vector register allocation in TCG now, so
using 7 registers is feasible and will not have a major impact on code
generation.
This patch:
1. Reserves vector register 0 for use as a mask register.
2. When using register groups, reserves the additional registers within
each group.
Signed-off-by: Huang Shiyuan <[email protected]>
Co-authored-by: TANG Tiancheng <[email protected]>
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d4be6ee111118e7f15644bc33ec8995dd610c68e
https://github.com/qemu/qemu/commit/d4be6ee111118e7f15644bc33ec8995dd610c68e
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Implement vector mov/dup{m/i}
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5a63f5998791460342ddc1fcd74db5909d00a2b9
https://github.com/qemu/qemu/commit/5a63f5998791460342ddc1fcd74db5909d00a2b9
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Add support for basic vector opcodes
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a31768c0192a6f1f62d07c4985a77814be34a915
https://github.com/qemu/qemu/commit/a31768c0192a6f1f62d07c4985a77814be34a915
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector cmp/cmpsel ops
Extend comparison results from mask registers to SEW-width elements,
following recommendations in The RISC-V SPEC Volume I (Version 20240411).
This aligns with TCG's cmp_vec behavior by expanding compare results to
full element width: all 1s for true, all 0s for false.
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c283c0748a01ec05f24d5aa24409f42b459e8938
https://github.com/qemu/qemu/commit/c283c0748a01ec05f24d5aa24409f42b459e8938
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector neg ops
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: dc9cd4ec12074a762ca9f41a822a27aa702284d4
https://github.com/qemu/qemu/commit/dc9cd4ec12074a762ca9f41a822a27aa702284d4
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Accept constant first argument to sub_vec
Use vrsub.vi to subtract from a constant.
Reviewed-by: LIU Zhiwei <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 101c1ef56221926718eb70d33ac2844d139d55e0
https://github.com/qemu/qemu/commit/101c1ef56221926718eb70d33ac2844d139d55e0
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector sat/mul ops
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1631f19b04fe29ba6c3c75a8c6decd3856da4853
https://github.com/qemu/qemu/commit/1631f19b04fe29ba6c3c75a8c6decd3856da4853
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector min/max ops
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cbde22f18bc7a7c16f5db1dda9030cb4786fb5f6
https://github.com/qemu/qemu/commit/cbde22f18bc7a7c16f5db1dda9030cb4786fb5f6
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector shi/s/v ops
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d1843219a1365f92ac1652074ba8c352eeeff82f
https://github.com/qemu/qemu/commit/d1843219a1365f92ac1652074ba8c352eeeff82f
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement vector roti/v/x ops
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4b7868f8c21cebda86e81f3653e055aa2e87b591
https://github.com/qemu/qemu/commit/4b7868f8c21cebda86e81f3653e055aa2e87b591
Author: TANG Tiancheng <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Enable native vector support for TCG host
Signed-off-by: TANG Tiancheng <[email protected]>
Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9a2a5f1b63b11d22a95d3ff800cf7eb5233254e2
https://github.com/qemu/qemu/commit/9a2a5f1b63b11d22a95d3ff800cf7eb5233254e2
Author: Dani Szebenyi <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Fix tcg_out_rlw_rc
The TCG IR sequence:
mov_i32 tmp97,$0xc4240000 dead: 1 pref=0xffffffff
mov_i32 tmp98,$0x0 pref=0xffffffff
rotr_i32 tmp97,tmp97,tmp98 dead: 1 2 pref=0xffffffff
was translated to `slwi r15, r14, 0` instead of `slwi r14, r14, 0`
due to SH field overflow. SH field is 5 bits, and tcg_out_rlw is called
in some situations with `32-n`, when `n` is 0 it results in an overflow
to RA field.
This commit prevents overflow of that field and adds debug assertions
for the other fields
Acked-by: Ilya Leoshkevich <[email protected]>
Signed-off-by: Dani Szebenyi <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4a75c8c7d6d1a965a1ef0a8067d0af9364edb800
https://github.com/qemu/qemu/commit/4a75c8c7d6d1a965a1ef0a8067d0af9364edb800
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M include/exec/exec-all.h
Log Message:
-----------
include/exec: Improve probe_access_full{, _mmu} documentation
Suggested-by: Alex Bennée <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: b56617bbcb473c25815d1bf475e326f84563b1de
https://github.com/qemu/qemu/commit/b56617bbcb473c25815d1bf475e326f84563b1de
Author: Alexander Graf <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Walk NPT in guest real mode
When translating virtual to physical address with a guest CPU that
supports nested paging (NPT), we need to perform every page table walk
access indirectly through the NPT, which we correctly do.
However, we treat real mode (no page table walk) special: In that case,
we currently just skip any walks and translate VA -> PA. With NPT
enabled, we also need to then perform NPT walk to do GVA -> GPA -> HPA
which we fail to do so far.
The net result of that is that TCG VMs with NPT enabled that execute
real mode code (like SeaBIOS) end up with GPA==HPA mappings which means
the guest accesses host code and data. This typically shows as failure
to boot guests.
This patch changes the page walk logic for NPT enabled guests so that we
always perform a GVA -> GPA translation and then skip any logic that
requires an actual PTE.
That way, all remaining logic to walk the NPT stays and we successfully
walk the NPT in real mode.
Cc: [email protected]
Fixes: fe441054bb3f0 ("target-i386: Add NPT support")
Signed-off-by: Alexander Graf <[email protected]>
Reported-by: Eduard Vlad <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 115ade42d50144c15b74368d32dc734ea277d853
https://github.com/qemu/qemu/commit/115ade42d50144c15b74368d32dc734ea277d853
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Use probe_access_full_mmu in ptw_translate
The probe_access_full_mmu function was designed for this purpose,
and does not report the memory operation event to plugins.
Cc: [email protected]
Fixes: 6d03226b422 ("plugins: force slow path when plugins instrument memory
ops")
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: e46fbc7d50289a9316fb582f4f98248bc642309e
https://github.com/qemu/qemu/commit/e46fbc7d50289a9316fb582f4f98248bc642309e
Author: Richard Henderson <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Remove ra parameter from ptw_translate
This argument is no longer used.
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: bbd5630a75e70a0f1bcf04de74c94aa94a145628
https://github.com/qemu/qemu/commit/bbd5630a75e70a0f1bcf04de74c94aa94a145628
Author: Ilya Leoshkevich <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Emulate /proc/self/maps under mmap_lock
If one thread modifies the mappings and another thread prints them,
a situation may occur that the printer thread sees a guest mapping
without a corresponding host mapping, leading to a crash in
open_self_maps_2().
Cc: [email protected]
Fixes: 7b7a3366e142 ("linux-user: Use walk_memory_regions for open_self_maps")
Signed-off-by: Ilya Leoshkevich <[email protected]>
Reviewed-by: Laurent Vivier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8704132805cf7a3259d1c5a073b3c2b92afa2616
https://github.com/qemu/qemu/commit/8704132805cf7a3259d1c5a073b3c2b92afa2616
Author: Ilya Leoshkevich <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M linux-user/ppc/signal.c
Log Message:
-----------
linux-user/ppc: Fix sigmask endianness issue in sigreturn
do_setcontext() copies the target sigmask without endianness handling
and then uses target_to_host_sigset_internal(), which expects a
byte-swapped one. Use target_to_host_sigset() instead.
Fixes: bcd4933a23f1 ("linux-user: ppc signal handling")
Signed-off-by: Ilya Leoshkevich <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f769eb00b5d7475eded925a6b8b93f45d6bc05ea
https://github.com/qemu/qemu/commit/f769eb00b5d7475eded925a6b8b93f45d6bc05ea
Author: Ilya Leoshkevich <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M linux-user/strace.c
M linux-user/strace.list
Log Message:
-----------
linux-user: Trace rt_sigprocmask's sigsets
Add a function for formatting target sigsets. It can be useful for
other syscalls in the future, so put it into the beginning of strace.c.
For simplicity, do not implement the strace's ~[] output syntax.
Add a rt_sigprocmask return handler.
Example outputs:
753914 rt_sigprocmask(SIG_BLOCK,[SIGCHLD SIGTSTP SIGTTIN
SIGTTOU],0x00007f80fddfe380,8) = 0 (oldset=[SIGTTOU])
753914 rt_sigprocmask(SIG_SETMASK,[SIGCHLD],NULL,8) = 0
753914 rt_sigprocmask(SIG_BLOCK,NULL,0x00007f80fddff3c0,8) = 0 (oldset=[])
Signed-off-by: Ilya Leoshkevich <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c12df59de99c7e7e79586cfe1ca4a8e50ff04cbc
https://github.com/qemu/qemu/commit/c12df59de99c7e7e79586cfe1ca4a8e50ff04cbc
Author: Yao Zi <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M linux-user/syscall_defs.h
Log Message:
-----------
linux-user: Fix build failure caused by missing __u64 on musl
Commit 9651cead2f ("linux-user: add openat2 support in linux-user")
ships a definition of struct open_how_ver0 while assuming type __u64 is
available in code, which is not the case when building QEMU on musl.
Let's replaces __u64 with uint64_t.
Fixes: 9651cead2f ("linux-user: add openat2 support in linux-user")
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Laurent Vivier <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 310df7a9fe400f32cde8a7edf80daad12cd9cf02
https://github.com/qemu/qemu/commit/310df7a9fe400f32cde8a7edf80daad12cd9cf02
Author: Yao Zi <[email protected]>
Date: 2024-10-22 (Tue, 22 Oct 2024)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN
Current definition yields a negative 32bits value, messing up hwprobe
result when Zvfhmin extension presents. Replace it by using a 1ULL bit
shift value as done in kernel upstream.
Link:
https://github.com/torvalds/linux/commit/5ea6764d9095e234b024054f75ebbccc4f0eb146
Fixes: a3432cf227 ("linux-user/riscv: Sync hwprobe keys with Linux")
Cc: [email protected]
Signed-off-by: Yao Zi <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9f4278837dc770266c8a026696dd91a525dd2682
https://github.com/qemu/qemu/commit/9f4278837dc770266c8a026696dd91a525dd2682
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/bootmap.h
M pc-bios/s390-ccw/cio.c
M pc-bios/s390-ccw/dasd-ipl.c
M pc-bios/s390-ccw/jump2ipl.c
R pc-bios/s390-ccw/libc.c
R pc-bios/s390-ccw/libc.h
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/menu.c
M pc-bios/s390-ccw/netboot.mak
M pc-bios/s390-ccw/netmain.c
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/sclp.c
M pc-bios/s390-ccw/virtio-blkdev.c
M pc-bios/s390-ccw/virtio-scsi.c
M pc-bios/s390-ccw/virtio.c
M tests/tcg/s390x/Makefile.softmmu-target
M tests/tcg/s390x/console.c
Log Message:
-----------
pc-bios/s390-ccw: Use the libc from SLOF and remove sclp prints
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple implementation that we currently use for the s390-ccw.img binary.
Since we are now always assuming that the SLOF submodule is available
when building the s390-ccw bios (see commit bf6903f6944f), we can drop
the simple implementation and use the SLOF libc for the s390-ccw.img
binary, too.
Additionally replace sclp_print calls with puts/printf now that it is
available.
Co-authored by: Thomas Huth <[email protected]>
Signed-off-by: Jared Rossi <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 8e5739ce4b0b04d7121cb2b29521acde2a8f3a24
https://github.com/qemu/qemu/commit/8e5739ce4b0b04d7121cb2b29521acde2a8f3a24
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/cio.h
M pc-bios/s390-ccw/iplb.h
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/netboot.mak
M pc-bios/s390-ccw/netmain.c
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/virtio.h
Log Message:
-----------
pc-bios/s390-ccw: Link the netboot code into the main s390-ccw.img binary
We originally built a separate binary for the netboot code since it
was considered as experimental and we could not be sure that the
necessary SLOF module had been checked out. Time passed, the code
proved its usefulness, and the build system nowadays makes sure that
the SLOF module is checked out if you have a s390x compiler available
for building the s390-ccw bios. So there is no real compelling reason
anymore to keep the netboot code in a separate binary. Linking the
code together with the main s390-ccw.img will make future enhancements
much easier, like supporting more than one boot device.
Co-authored by: Thomas Huth <[email protected]>
Signed-off-by: Jared Rossi <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 188e255bf8ed68fa64bcb63577cb100eeb326254
https://github.com/qemu/qemu/commit/188e255bf8ed68fa64bcb63577cb100eeb326254
Author: Thomas Huth <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/s390x/ipl.c
M hw/s390x/ipl.h
M hw/s390x/s390-virtio-ccw.c
M pc-bios/meson.build
R pc-bios/s390-netboot.img
Log Message:
-----------
hw/s390x: Remove the possibility to load the s390-netboot.img binary
Since the netboot code has now been merged into the main s390-ccw.img
binary, we don't need the separate s390-netboot.img anymore. Remove
it and the code that was responsible for loading it.
Message-Id: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: f1fdadda36f73c9a4a96f92deb3062528cd12acc
https://github.com/qemu/qemu/commit/f1fdadda36f73c9a4a96f92deb3062528cd12acc
Author: Thomas Huth <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/Makefile
R pc-bios/s390-ccw/netboot.mak
Log Message:
-----------
pc-bios/s390-ccw: Merge netboot.mak into the main Makefile
Now that the netboot code has been merged into the main s390-ccw.img,
it also does not make sense to keep the build rules in a separate
file. Thus let's merge netboot.mak into the main Makefile.
Message-Id: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: ab2691b6c7ff360875e0af86ff463278f17786f5
https://github.com/qemu/qemu/commit/ab2691b6c7ff360875e0af86ff463278f17786f5
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M docs/system/s390x/bootdevices.rst
Log Message:
-----------
docs/system/s390x/bootdevices: Update the documentation about network booting
Remove the information about the separate s390-netboot.img from
the documentation.
Co-authored by: Thomas Huth <[email protected]>
Signed-off-by: Jared Rossi <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: bef2b8dd1a36fc79cabcda48e667f2cba476924c
https://github.com/qemu/qemu/commit/bef2b8dd1a36fc79cabcda48e667f2cba476924c
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/bootmap.h
M pc-bios/s390-ccw/s390-ccw.h
Log Message:
-----------
pc-bios/s390-ccw: Remove panics from ISO IPL path
Remove panic-on-error from IPL ISO El Torito specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 806315279d5c629e1cc3a945bcfba3fe5482d84b
https://github.com/qemu/qemu/commit/806315279d5c629e1cc3a945bcfba3fe5482d84b
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/bootmap.h
Log Message:
-----------
pc-bios/s390-ccw: Remove panics from ECKD IPL path
Remove panic-on-error from ECKD block device IPL specific functions so that
error recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: facd91ac1af75b657fc80189fe9cb026bb1abdbc
https://github.com/qemu/qemu/commit/facd91ac1af75b657fc80189fe9cb026bb1abdbc
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/virtio-blkdev.c
M pc-bios/s390-ccw/virtio-scsi.c
Log Message:
-----------
pc-bios/s390-ccw: Remove panics from SCSI IPL path
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 1d5c7f078e938e6844f404429dd70bc52b39dac6
https://github.com/qemu/qemu/commit/1d5c7f078e938e6844f404429dd70bc52b39dac6
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/dasd-ipl.c
M pc-bios/s390-ccw/dasd-ipl.h
Log Message:
-----------
pc-bios/s390-ccw: Remove panics from DASD IPL path
Remove panic-on-error from DASD IPL specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: f1a2a6e41ef76e02ddc5ede3dd042ef96b4fb8d2
https://github.com/qemu/qemu/commit/f1a2a6e41ef76e02ddc5ede3dd042ef96b4fb8d2
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/netmain.c
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/virtio-net.c
Log Message:
-----------
pc-bios/s390-ccw: Remove panics from Netboot IPL path
Remove panic-on-error from Netboot specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 0181e23713114fd4c33326c3372aaf48dcfb412a
https://github.com/qemu/qemu/commit/0181e23713114fd4c33326c3372aaf48dcfb412a
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/cio.c
M pc-bios/s390-ccw/jump2ipl.c
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/virtio-blkdev.c
M pc-bios/s390-ccw/virtio.c
M pc-bios/s390-ccw/virtio.h
Log Message:
-----------
pc-bios/s390-ccw: Enable failed IPL to return after error
Remove panic-on-error from IPL functions such that a return code is propagated
back to the main IPL calling function (rather than terminating immediately),
which facilitates possible error recovery in the future.
A select few panics remain, which indicate fatal non-devices errors that must
result in termination.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: ba3658adc80a9370257a9c4e114829ec691311e3
https://github.com/qemu/qemu/commit/ba3658adc80a9370257a9c4e114829ec691311e3
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/s390x/ipl.h
A include/hw/s390x/ipl/qipl.h
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/iplb.h
Log Message:
-----------
include/hw/s390x: Add include files for common IPL structs
Currently, structures defined in both hw/s390x/ipl.h and pc-bios/s390-ccw/iplb.h
must be kept in sync, which is prone to error. Instead, create a new directory
at include/hw/s390x/ipl/ to contain the definitions that must be shared.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: bb185de42339025db9bbd5aa11f3f644c2a077f8
https://github.com/qemu/qemu/commit/bb185de42339025db9bbd5aa11f3f644c2a077f8
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/s390x/ccw-device.c
M hw/s390x/ccw-device.h
M hw/s390x/ipl.c
M hw/s390x/ipl.h
M hw/s390x/s390-virtio-ccw.c
M hw/s390x/sclp.c
M include/hw/s390x/ipl/qipl.h
M pc-bios/s390-ccw/main.c
Log Message:
-----------
s390x: Add individual loadparm assignment to CCW device
Add a loadparm property to the VirtioCcwDevice object so that different
loadparms can be defined on a per-device basis for CCW boot devices.
The machine/global loadparm is still supported. If both a global and per-device
loadparm are defined, the per-device value will override the global value for
that device, but any other devices that do not specify a per-device loadparm
will still use the global loadparm.
It is invalid to assign a loadparm to a non-boot device.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 0927875e704e93ace03bb7533c0877bf97e4bda9
https://github.com/qemu/qemu/commit/0927875e704e93ace03bb7533c0877bf97e4bda9
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/s390x/ipl.c
M hw/s390x/ipl.h
M include/hw/s390x/ipl/qipl.h
Log Message:
-----------
hw/s390x: Build an IPLB for each boot device
Build an IPLB for any device with a bootindex (up to a maximum of 8 devices).
The IPLB chain is placed immediately before the BIOS in memory. Because this
is not a fixed address, the location of the next IPLB and number of remaining
boot devices is stored in the QIPL global variable for possible later access by
the guest during IPL.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
[thuth: Fix endianness problem when accessing the qipl structure]
Signed-off-by: Thomas Huth <[email protected]>
Commit: 455e3bc3f74ee76964efec2e0c646db15095d0d2
https://github.com/qemu/qemu/commit/455e3bc3f74ee76964efec2e0c646db15095d0d2
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/s390x/ipl.c
M hw/s390x/ipl.h
M include/hw/s390x/ipl/qipl.h
M pc-bios/s390-ccw/jump2ipl.c
M target/s390x/diag.c
Log Message:
-----------
s390x: Rebuild IPLB for SCSI device directly from DIAG308
Because virtio-scsi type devices use a non-architected IPLB pbt code they cannot
be set and stored normally. Instead, the IPLB must be rebuilt during re-ipl.
As s390x does not natively support multiple boot devices, the devno field is
used to store the position in the boot order for the device.
Handling the rebuild as part of DIAG308 removes the need to check the devices
for invalid IPLBs later in the IPL.
Signed-off-by: Jared Rossi <[email protected]>
Acked-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: f697bed22f58eff9b2893ac2fe3d511847398400
https://github.com/qemu/qemu/commit/f697bed22f58eff9b2893ac2fe3d511847398400
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/iplb.h
M pc-bios/s390-ccw/jump2ipl.c
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/netmain.c
Log Message:
-----------
pc-bios/s390x: Enable multi-device boot loop
Allow attempts to boot from multiple IPL devices. If the first device fails to
IPL, select the pre-built IPLB for the next device in the boot order and attempt
to IPL from it. Continue this process until IPL is successful or there are no
devices left to try.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 0bd107138ff0b171e3cd314dbc200950bcab2b05
https://github.com/qemu/qemu/commit/0bd107138ff0b171e3cd314dbc200950bcab2b05
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M docs/system/bootindex.rst
M docs/system/s390x/bootdevices.rst
Log Message:
-----------
docs/system: Update documentation for s390x IPL
Update docs to show that s390x PC BIOS can support more than one boot device.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: f5aa2d9d4c6480fa73b89c935050afe57e5d8bd9
https://github.com/qemu/qemu/commit/f5aa2d9d4c6480fa73b89c935050afe57e5d8bd9
Author: Jared Rossi <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M tests/qtest/cdrom-test.c
Log Message:
-----------
tests/qtest: Add s390x boot order tests to cdrom-test.c
Add two new qtests to verify that a valid IPL device can successfully boot after
failed IPL attempts from one or more invalid devices.
cdrom-test/as-fallback-device: Defines the primary boot target as a device that
is invalid for IPL and a second boot target that is valid for IPL. Ensures that
the valid device will be selected after the initial failed IPL.
cdrom-test/as-last-option: Defines the maximum number of boot devices (8)
where only the final entry in the boot order is valid. Ensures that a valid
device will be selected even after multiple failed IPL attempts from both
virtio-blk and virtio-scsi device types.
Signed-off-by: Jared Rossi <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: c58df213af7ec8924d219025a593b8f3ac475f16
https://github.com/qemu/qemu/commit/c58df213af7ec8924d219025a593b8f3ac475f16
Author: Jens Remus <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/start.S
Log Message:
-----------
pc-bios/s390-ccw: Clarify alignment is in bytes
The assembler directive .align [1] has architecture-dependent behavior,
which may be ambiguous for the reader. Some architectures perform the
alignment in bytes, others in power of two. s390 does in bytes.
Use the directive .balign [2] instead, to clarify that the alignment
request is in bytes. No functional change.
[1] https://sourceware.org/binutils/docs/as/Align.html
[2] https://sourceware.org/binutils/docs/as/Balign.html
Signed-off-by: Jens Remus <[email protected]>
Reviewed-by: Marc Hartmayer <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 3259b4424a85d9cdfd1a33ed6030a6c51c1b9b8b
https://github.com/qemu/qemu/commit/3259b4424a85d9cdfd1a33ed6030a6c51c1b9b8b
Author: Jens Remus <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/start.S
Log Message:
-----------
pc-bios/s390-ccw: Don't generate TEXTRELs
Commit 7cd50cbe4ca3 ("pc-bios/s390-ccw: Don't use __bss_start with the
"larl" instruction") introduced the address constant bss_start_literal
for __bss_start in the .text section, which introduced a relocation in
code (i.e. TEXTREL). The dedicated constant is required, as __bss_start
may not necessarily be aligned on a 2-byte boundary (see subject commit
for details).
Move the constant to the .data section to get rid of the relocation in
the .text section. Add the linker option -z text to prevent TEXTRELs to
get introduced in the future.
Note that the R_390_RELATIVE relocations are taken care of by function
glue() in include/hw/elf_ops.h.inc introduced by commit 5dce07e1cb67
("elf-loader: Provide the possibility to relocate s390 ELF files").
Reported-by: Marc Hartmayer <[email protected]>
Signed-off-by: Jens Remus <[email protected]>
Reviewed-by: Marc Hartmayer <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 694d79ffce996c0993cebccc07c2ab6fc281e7d0
https://github.com/qemu/qemu/commit/694d79ffce996c0993cebccc07c2ab6fc281e7d0
Author: Marc Hartmayer <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw/Makefile
Log Message:
-----------
pc-bios/s390-ccw: Introduce `EXTRA_LDFLAGS`
Some packaging tools want to override `LDFLAGS` when building QEMU, this will
result in a build error as most likely no `-nostdlib` flag is passed. Introduce
`EXTRA_LDFLAGS` so that the packager can override `LDFLAGS` without breaking the
build.
Signed-off-by: Marc Hartmayer <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
[thuth: Drop the hunk to netbook.mak which is not necessary anymore]
Signed-off-by: Thomas Huth <[email protected]>
Commit: 239e351ec415ff3673d9da70d70ca3a5dd95a2f0
https://github.com/qemu/qemu/commit/239e351ec415ff3673d9da70d70ca3a5dd95a2f0
Author: Thomas Huth <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M pc-bios/s390-ccw.img
Log Message:
-----------
pc-bios/s390-ccw: Update s390-ccw.img with the full boot order support feature
This update includes the full boot order support feature from Jared Rossi
and the TEXTREL fix from Jens Remus.
Signed-off-by: Thomas Huth <[email protected]>
Commit: 6b3756503b00d42f1f506815b44ce83aa23ee322
https://github.com/qemu/qemu/commit/6b3756503b00d42f1f506815b44ce83aa23ee322
Author: Peter Maydell <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M disas/riscv.c
M disas/riscv.h
M host/include/riscv/host/cpuinfo.h
M include/exec/exec-all.h
M include/tcg/tcg.h
M linux-user/ppc/signal.c
M linux-user/strace.c
M linux-user/strace.list
M linux-user/syscall.c
M linux-user/syscall_defs.h
M target/i386/tcg/sysemu/excp_helper.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
A tcg/riscv/tcg-target.opc.h
M tcg/tcg.c
M util/cpuinfo-riscv.c
Log Message:
-----------
Merge tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu into staging
tcg: Reset data_gen_ptr correctly
tcg/riscv: Implement host vector support
tcg/ppc: Fix tcg_out_rlw_rc
target/i386: Walk NPT in guest real mode
target/i386: Use probe_access_full_mmu in ptw_translate
linux-user: Fix build failure caused by missing __u64 on musl
linux-user: Emulate /proc/self/maps under mmap_lock
linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN
linux-user/ppc: Fix sigmask endianness issue in sigreturn
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# 18K6nfAXXT+Zm0IrJMey/7b1jUWF3nMUVCTuLvmhSOwBAkIvTVYHko9CjvLtM6YH
# UHu3yA==
# =V393
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 23 Oct 2024 04:30:15 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu: (24 commits)
linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN
linux-user: Fix build failure caused by missing __u64 on musl
linux-user: Trace rt_sigprocmask's sigsets
linux-user/ppc: Fix sigmask endianness issue in sigreturn
linux-user: Emulate /proc/self/maps under mmap_lock
target/i386: Remove ra parameter from ptw_translate
target/i386: Use probe_access_full_mmu in ptw_translate
target/i386: Walk NPT in guest real mode
include/exec: Improve probe_access_full{, _mmu} documentation
tcg/ppc: Fix tcg_out_rlw_rc
tcg/riscv: Enable native vector support for TCG host
tcg/riscv: Implement vector roti/v/x ops
tcg/riscv: Implement vector shi/s/v ops
tcg/riscv: Implement vector min/max ops
tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Accept constant first argument to sub_vec
tcg/riscv: Implement vector neg ops
tcg/riscv: Implement vector cmp/cmpsel ops
tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Implement vector mov/dup{m/i}
...
Signed-off-by: Peter Maydell <[email protected]>
Commit: e17e57e862faf6e1f372385c18dcf6d3fd31158e
https://github.com/qemu/qemu/commit/e17e57e862faf6e1f372385c18dcf6d3fd31158e
Author: Peter Maydell <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M docs/system/bootindex.rst
M docs/system/s390x/bootdevices.rst
M hw/s390x/ccw-device.c
M hw/s390x/ccw-device.h
M hw/s390x/ipl.c
M hw/s390x/ipl.h
M hw/s390x/s390-virtio-ccw.c
M hw/s390x/sclp.c
A include/hw/s390x/ipl/qipl.h
M pc-bios/meson.build
M pc-bios/s390-ccw.img
M pc-bios/s390-ccw/Makefile
M pc-bios/s390-ccw/bootmap.c
M pc-bios/s390-ccw/bootmap.h
M pc-bios/s390-ccw/cio.c
M pc-bios/s390-ccw/cio.h
M pc-bios/s390-ccw/dasd-ipl.c
M pc-bios/s390-ccw/dasd-ipl.h
M pc-bios/s390-ccw/iplb.h
M pc-bios/s390-ccw/jump2ipl.c
R pc-bios/s390-ccw/libc.c
R pc-bios/s390-ccw/libc.h
M pc-bios/s390-ccw/main.c
M pc-bios/s390-ccw/menu.c
R pc-bios/s390-ccw/netboot.mak
M pc-bios/s390-ccw/netmain.c
M pc-bios/s390-ccw/s390-ccw.h
M pc-bios/s390-ccw/sclp.c
M pc-bios/s390-ccw/start.S
M pc-bios/s390-ccw/virtio-blkdev.c
M pc-bios/s390-ccw/virtio-net.c
M pc-bios/s390-ccw/virtio-scsi.c
M pc-bios/s390-ccw/virtio.c
M pc-bios/s390-ccw/virtio.h
R pc-bios/s390-netboot.img
M target/s390x/diag.c
M tests/qtest/cdrom-test.c
M tests/tcg/s390x/Makefile.softmmu-target
M tests/tcg/s390x/console.c
Log Message:
-----------
Merge tag 'pull-request-2024-10-23' of https://gitlab.com/thuth/qemu into
staging
* Allow multiple boot devices (via bootindex properties) on s390x
* Avoid TEXTREL relocations in the s390-ccw.img firmware
# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmcY9vsRHHRodXRoQHJl
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# woazKmHz7Hu6uS5+JPtfD+KxalIDXNXevY6uGyaWJp8TahDkUCim/gJ+Zb7Mx1iq
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# 0EI+x1fxW1w=
# =mWW5
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 23 Oct 2024 14:15:39 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "[email protected]"
# gpg: Good signature from "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2024-10-23' of https://gitlab.com/thuth/qemu: (23 commits)
pc-bios/s390-ccw: Update s390-ccw.img with the full boot order support feature
pc-bios/s390-ccw: Introduce `EXTRA_LDFLAGS`
pc-bios/s390-ccw: Don't generate TEXTRELs
pc-bios/s390-ccw: Clarify alignment is in bytes
tests/qtest: Add s390x boot order tests to cdrom-test.c
docs/system: Update documentation for s390x IPL
pc-bios/s390x: Enable multi-device boot loop
s390x: Rebuild IPLB for SCSI device directly from DIAG308
hw/s390x: Build an IPLB for each boot device
s390x: Add individual loadparm assignment to CCW device
include/hw/s390x: Add include files for common IPL structs
pc-bios/s390-ccw: Enable failed IPL to return after error
pc-bios/s390-ccw: Remove panics from Netboot IPL path
pc-bios/s390-ccw: Remove panics from DASD IPL path
pc-bios/s390-ccw: Remove panics from SCSI IPL path
pc-bios/s390-ccw: Remove panics from ECKD IPL path
pc-bios/s390-ccw: Remove panics from ISO IPL path
docs/system/s390x/bootdevices: Update the documentation about network booting
pc-bios/s390-ccw: Merge netboot.mak into the main Makefile
hw/s390x: Remove the possibility to load the s390-netboot.img binary
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/e67b7aef7c7f...e17e57e862fa
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