Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3035be4c7268dd50e48cec4612eaaa19daa1645c
https://github.com/qemu/qemu/commit/3035be4c7268dd50e48cec4612eaaa19daa1645c
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M .gitlab-ci.d/cirrus.yml
R .gitlab-ci.d/cirrus/macos-15.vars
M tests/lcitool/refresh
Log Message:
-----------
.gitlab-ci.d/cirrus: Remove the macos-15 job
Cirrus-CI stopped providing the possibility to run macOS 15 jobs.
Quoting https://cirrus-ci.org/guide/macOS/ :
"Cirrus CI Cloud only allows ghcr.io/cirruslabs/macos-runner:sonoma image ..."
If you still try to run a Sequoia image, it gets automatically "upgraded"
to Sonoma instead. So the macos-15 job in the QEMU CI now does not
make sense anymore, thus let's remove it.
Message-ID: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Acked-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 918d369540a847443aab321f53079fb66e8384ee
https://github.com/qemu/qemu/commit/918d369540a847443aab321f53079fb66e8384ee
Author: Daniel P. Berrangé <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/functional/qemu_test/tuxruntest.py
Log Message:
-----------
tests/functional: make tuxrun disk images writable
The zstd command will preserve the input archive permissions on the
output file. So when we decompress the readonly cached image, the
resulting per-test run private disk image will also be readonly.
We need it to be writable, so make it so.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 3f4a28860ab3e6e58944288da804418ba303dbeb
https://github.com/qemu/qemu/commit/3f4a28860ab3e6e58944288da804418ba303dbeb
Author: Daniel P. Berrangé <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/functional/qemu_test/asset.py
Log Message:
-----------
tests/functional: make cached asset files read-only
This ensures that if a functional test runs QEMU with a writable
disk pointing to a cached asset, an error will be reported, rather
than silently modifying the cache file.
As an example, tweaking test_sbsaref.py to set snapshot=off,
results in a clear error:
Command: ./build/qemu-system-aarch64 ...snip... -drive
file=/var/home/berrange/.cache/qemu/download/44cdbae275ef1bb6dab1d5fbb59473d4f741e1c8ea8a80fd9e906b531d6ad461,format=raw,snapshot=off
-cpu max,pauth=off
Output: qemu-system-aarch64: Could not open
'/var/home/berrange/.cache/qemu/download/44cdbae275ef1bb6dab1d5fbb59473d4f741e1c8ea8a80fd9e906b531d6ad461':
Permission denied
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 6a181653748b3d9158a80931113b77964736ce1f
https://github.com/qemu/qemu/commit/6a181653748b3d9158a80931113b77964736ce1f
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/cirrus.yml
M .gitlab-ci.d/crossbuilds.yml
M .travis.yml
A configs/devices/sh4eb-softmmu/default.mak
A configs/targets/sh4eb-softmmu.mak
M qapi/machine.json
M tests/qemu-iotests/testenv.py
M tests/qtest/endianness-test.c
M tests/qtest/machine-none-test.c
M tests/qtest/meson.build
Log Message:
-----------
Revert "Remove the unused sh4eb target"
This reverts commit 73ceb12960e686b763415f0880cc5171ccce01cf.
The "r2d" machine can work in big endian mode, see:
https://lore.kernel.org/qemu-devel/[email protected]/
So the reasoning for removing sh4eb was wrong.
Message-ID: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Rob Landley <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: f596d628250e0d77cc9d6f57c6d126dcfbb739d6
https://github.com/qemu/qemu/commit/f596d628250e0d77cc9d6f57c6d126dcfbb739d6
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/functional/meson.build
A tests/functional/test_sh4eb_r2d.py
Log Message:
-----------
tests/functional: Add a test for sh4eb
Now that we are aware of binaries that are available for sh4eb,
we should make sure that there are no regressions with this
target and test it regularly in our CI.
Message-ID: <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 33c469ee1dfb42ea90ccdfb28a78eee0b641b541
https://github.com/qemu/qemu/commit/33c469ee1dfb42ea90ccdfb28a78eee0b641b541
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/vm/openbsd
Log Message:
-----------
tests/vm/openbsd: Remove the "Time appears wrong" workaround
Seems like the server now reports the right time again, so we have
to drop the workaround to get the installer working again.
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: d411269b4d4ac851622fb79eefb1d12580cb9fcc
https://github.com/qemu/qemu/commit/d411269b4d4ac851622fb79eefb1d12580cb9fcc
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/functional/meson.build
M tests/functional/test_ppc64_tuxrun.py
Log Message:
-----------
tests/functional: Fix the s390x and ppc64 tuxrun tests
I forgot to add the tests to the meson.build file and looks
like I even managed to somehow mix up the hashsums in the
ppc64 test!
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: c63f19f455550bfaeb443deb516f21617914ed4c
https://github.com/qemu/qemu/commit/c63f19f455550bfaeb443deb516f21617914ed4c
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M hw/s390x/Kconfig
Log Message:
-----------
hw/s390x: Re-enable the pci-bridge device on s390x
Commit e779e5c05a ("hw/pci-bridge: Add a Kconfig switch for the
normal PCI bridge") added a config switch for the pci-bridge, so
that the device is not included in the s390x target anymore (since
the pci-bridge is not really useful on s390x).
However, it seems like libvirt is still adding pci-bridge devices
automatically to the guests' XML definitions (when adding a PCI
device to a non-zero PCI bus), so these guests are now broken due
to the missing pci-bridge in the QEMU binary.
To avoid disruption of the users, let's re-enable the pci-bridge
device on s390x for the time being.
Message-ID: <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Boris Fiuczynski <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 26587ff4db908894f0a0ca30689c3b7b285c7ce4
https://github.com/qemu/qemu/commit/26587ff4db908894f0a0ca30689c3b7b285c7ce4
Author: Mark Cave-Ayland <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M hw/m68k/next-cube.c
Log Message:
-----------
next-cube: fix up compilation when DEBUG_NEXT is enabled
These were accidentally introduced by my last series.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 94e10259f04ba90378ccb4919ac20f9b5493d744
https://github.com/qemu/qemu/commit/94e10259f04ba90378ccb4919ac20f9b5493d744
Author: Mark Cave-Ayland <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M hw/m68k/next-cube.c
Log Message:
-----------
next-cube: remove cpu parameter from next_scsi_init()
The parameter is not used.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: c3836e86db26ef980c005b029074ae5ae5a39dec
https://github.com/qemu/qemu/commit/c3836e86db26ef980c005b029074ae5ae5a39dec
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M MAINTAINERS
R tests/avocado/tcg_plugins.py
A tests/functional/test_aarch64_tcg_plugins.py
Log Message:
-----------
tests/functional: Convert the tcg_plugins test
A straight forward conversion, only the usual changes were required
here (i.e. adjustment for asset downloading, machine selection).
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: bf274caaabaab97ba629ee8ab4f763d88e0642c5
https://github.com/qemu/qemu/commit/bf274caaabaab97ba629ee8ab4f763d88e0642c5
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M tests/avocado/boot_linux_console.py
M tests/functional/meson.build
M tests/functional/qemu_test/utils.py
A tests/functional/test_arm_bpim2u.py
Log Message:
-----------
tests/functional: Convert BananaPi tests to the functional framework
Move the BananaPi tests from tests/avocado/boot_linux_console.py into
a new file dedicated for Banana Pi tests in the functional framework.
Update the hash sums of the assets to sha256 along the way and fix the
broken link for the buildroot image from storage.kernelci.org.
(Note: The test_arm_bpim2u_openwrt_22_03_3 test is currently broken
due to a regression in commit 4c2c047469 ("target/arm: Fix usage of MMU
indexes when EL3 is AArch32") - it works if that commit gets reverted)
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: ea27a2c8a56217187263deedecf5ba0635bb8725
https://github.com/qemu/qemu/commit/ea27a2c8a56217187263deedecf5ba0635bb8725
Author: Thomas Huth <[email protected]>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M MAINTAINERS
M tests/avocado/boot_linux_console.py
M tests/functional/meson.build
A tests/functional/test_arm_orangepi.py
Log Message:
-----------
tests/functional: Convert the OrangePi tests to the functional framework
Move the OrangePi tests from tests/avocado/boot_linux_console.py into
a new file dedicated for OrangePi tests in the functional framework
and update the hash sums of the assets to sha256 along the way.
For the buildroot image and the Armbian image, we've got to switch to
a newer version since the old images have been removed from the server,
and the NetBSD image has been moved to the archive, so we need to update
this URL as well.
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: 70f81c34d9d6e5c667e17f213c74cd0a36e5aaeb
https://github.com/qemu/qemu/commit/70f81c34d9d6e5c667e17f213c74cd0a36e5aaeb
Author: Yongbok Kim <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/sysemu/machine.c
Log Message:
-----------
target/mips: Migrate TLB MemoryMapID register
Include CP0 MemoryMapID register in migration state.
Fixes: 99029be1c28 ("target/mips: Add implementation of GINVT instruction")
Signed-off-by: Yongbok Kim <[email protected]>
Signed-off-by: Aleksandar Markovic <[email protected]>
Signed-off-by: Aleksandar Rakic <[email protected]>
Reviewed-by: Aleksandar Rikalo <[email protected]>
Message-ID:
<am9pr09mb4851fb6034edb7fa191ba47e84...@am9pr09mb4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 310bad465a4289f953ab6f5a20d9e83fdb5c4905
https://github.com/qemu/qemu/commit/310bad465a4289f953ab6f5a20d9e83fdb5c4905
Author: Aleksandar Markovic <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
-----------
target/mips: Enable MSA ASE for mips32r6-generic
Enable MSA ASE for mips32r6-generic CPU.
Signed-off-by: Aleksandar Markovic <[email protected]>
Signed-off-by: Faraz Shahbazker <[email protected]>
Signed-off-by: Aleksandar Rakic <[email protected]>
Reviewed-by: Aleksandar Rikalo <[email protected]>
Message-ID:
<am9pr09mb485153b7cb706e188ded763484...@am9pr09mb4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 085a28353d145099ae98c785e6884cfb967b1a8f
https://github.com/qemu/qemu/commit/085a28353d145099ae98c785e6884cfb967b1a8f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
target/mips: Extract decode_64bit_enabled() helper
Extract the decode_64bit_enabled() helper which detects
whether CPUs can run 64-bit instructions.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-Id: <[email protected]>
Commit: 7a6a57ff34bb8a9366b0ed66486ecc15d638213b
https://github.com/qemu/qemu/commit/7a6a57ff34bb8a9366b0ed66486ecc15d638213b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Simplify Loongson MULTU.G opcode
Since MULTU opcodes don't record the most significant bits
of the infinite result, sign-extending the sources make no
difference in the result.
Once we remove the sign extension of source registers, MULT
and MULTU are identical (as are DMULT and DMULTU).
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 25c71ee996ed9dcd66e0cc93e03535717c8d1ef6
https://github.com/qemu/qemu/commit/25c71ee996ed9dcd66e0cc93e03535717c8d1ef6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
There is no issue having multiple enum declarations with
the same value. As we are going to remove the OPC_MULT_G_2E
definition in few commits, restore the OPC_ADDUH_QB_DSP and
OPC_MUL_PH_DSP definitions and use them where they belong.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Jiaxun Yang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: a3c8fd895e759361c800b8078d30dfcc8089895c
https://github.com/qemu/qemu/commit/a3c8fd895e759361c800b8078d30dfcc8089895c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
A target/mips/tcg/godson2.decode
A target/mips/tcg/loong-ext.decode
A target/mips/tcg/loong_translate.c
M target/mips/tcg/meson.build
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
target/mips: Convert Loongson DDIV.G opcodes to decodetree
Introduce decode_loongson() to decode all Loongson vendor
specific opcodes. Start converting a single opcode: DDIV.G
(divide 64-bit signed integers).
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: f5a4499c46dfabf56d6d70d48f5d2e48ecb486fa
https://github.com/qemu/qemu/commit/f5a4499c46dfabf56d6d70d48f5d2e48ecb486fa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/godson2.decode
M target/mips/tcg/loong-ext.decode
M target/mips/tcg/loong_translate.c
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Convert Loongson DIV.G opcodes to decodetree
DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
'is_double' argument so it can generate DIV.G (divide 32-bit
signed integers).
With this commit we explicit the template used to generate
opcode for 32/64-bit word variants. Next commits will be less
verbose by providing both variants at once.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: d611a3906b39cb3919ee376f1cdc53d3f9b12239
https://github.com/qemu/qemu/commit/d611a3906b39cb3919ee376f1cdc53d3f9b12239
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/godson2.decode
M target/mips/tcg/loong-ext.decode
M target/mips/tcg/loong_translate.c
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
(divide 64-bit unsigned integers) opcodes to decodetree.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: eb5dff75be96014c0c3281e30150c48f4b5aae44
https://github.com/qemu/qemu/commit/eb5dff75be96014c0c3281e30150c48f4b5aae44
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/godson2.decode
M target/mips/tcg/loong-ext.decode
M target/mips/tcg/loong_translate.c
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
Convert the following opcodes to decodetree:
- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: e6e6cd284e79a26fcbeb6112be1c4d39363c629a
https://github.com/qemu/qemu/commit/e6e6cd284e79a26fcbeb6112be1c4d39363c629a
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/godson2.decode
M target/mips/tcg/loong-ext.decode
M target/mips/tcg/loong_translate.c
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
Convert the following opcodes to decodetree:
- MULT.G - multiply 32-bit signed integers
- MULTU.G - multiply 32-bit unsigned integers
- DMULT.G - multiply 64-bit signed integers
- DMULTU.G - multiply 64-bit unsigned integers
Now that all opcodes from the extension have been converted, we
can remove completely gen_loongson_integer() and its 2 calls in
decode_opc_special2_legacy() and decode_opc_special3_legacy().
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: a43ad643d4dc57286faa90e92389303ccba6e4f4
https://github.com/qemu/qemu/commit/a43ad643d4dc57286faa90e92389303ccba6e4f4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/tcg/loong_translate.c
Log Message:
-----------
target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
Loongson fixed-point multiplies and divisions opcodes are
specific to 64-bit cores (Loongson-2 and Loongson-3 families).
Simplify by removing the 32-bit checks.
Reported-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-Id: <[email protected]>
Commit: 601fb533eeabcfcbfda0511e6db30e77968859f7
https://github.com/qemu/qemu/commit/601fb533eeabcfcbfda0511e6db30e77968859f7
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.h
M target/mips/mips-defs.h
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Introduce ase_3d_available() helper
Determine if the MIPS-3D ASE is implemented by checking
the state of the 3D bit in the FIR CP1 control register.
Remove the then unused ASE_MIPS3D definition.
Note, this allows using MIPS-3D on the mips64dspr2 model.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 9a2b5bb9e56ce626d5c5584c4b30799d33fcf0c4
https://github.com/qemu/qemu/commit/9a2b5bb9e56ce626d5c5584c4b30799d33fcf0c4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
target/mips: Introduce disas_mt_available()
Similarly to commit 17c2c320f3c ("Introduce ase_mt_available helper"),
introduce the disas_mt_available() one which takes a DisasContext
argument to determine whether Multi-Threading is available by
checking the MT bit of the CP0_Config3 register.
Remove the then unused ASE_MT definition.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 7ec55c7d1729e97429e9d9d90f6604529050761f
https://github.com/qemu/qemu/commit/7ec55c7d1729e97429e9d9d90f6604529050761f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M target/mips/cpu.h
M target/mips/sysemu/machine.c
Log Message:
-----------
target/mips: Remove unused CPUMIPSState::current_fpu field
The 'current_fpu' field is unused since commit f01be154589
("Move the active FPU registers into env again, and use more
TCG registers to access them").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: d73ad1b1c0e62976d4790606ee29725a0d8a8906
https://github.com/qemu/qemu/commit/d73ad1b1c0e62976d4790606ee29725a0d8a8906
Author: Thomas Huth <[email protected]>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M MAINTAINERS
R tests/avocado/riscv_opensbi.py
M tests/functional/meson.build
A tests/functional/test_riscv_opensbi.py
Log Message:
-----------
tests/functional: Convert the riscv_opensbi avocado test into a standalone
test
The avocado test defined test functions for both, riscv32 and riscv64.
Since we can run the whole file with multiple targets in the new
framework, we can now consolidate the functions so we have to only
define one function per machine now.
Message-ID: <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 3acf0da364de981175cef24db16c721d3300c6ea
https://github.com/qemu/qemu/commit/3acf0da364de981175cef24db16c721d3300c6ea
Author: Peter Maydell <[email protected]>
Date: 2024-11-01 (Fri, 01 Nov 2024)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.h
M target/mips/mips-defs.h
M target/mips/sysemu/machine.c
A target/mips/tcg/godson2.decode
A target/mips/tcg/loong-ext.decode
A target/mips/tcg/loong_translate.c
M target/mips/tcg/meson.build
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
Merge tag 'mips-20241031' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Migrate missing CP0 TLB MemoryMapID register (Yongbok)
- Enable MSA ASE for mips32r6-generic (Aleksandar)
- Convert Loongson LEXT opcodes to decodetree (Philippe)
- Introduce ase_3d_available and disas_mt_available helpers (Philippe)
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# gpg: Signature made Thu 31 Oct 2024 04:29:06 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20241031' of https://github.com/philmd/qemu:
target/mips: Remove unused CPUMIPSState::current_fpu field
target/mips: Introduce disas_mt_available()
target/mips: Introduce ase_3d_available() helper
target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
target/mips: Convert Loongson DIV.G opcodes to decodetree
target/mips: Convert Loongson DDIV.G opcodes to decodetree
target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
target/mips: Simplify Loongson MULTU.G opcode
target/mips: Extract decode_64bit_enabled() helper
target/mips: Enable MSA ASE for mips32r6-generic
target/mips: Migrate TLB MemoryMapID register
Signed-off-by: Peter Maydell <[email protected]>
Commit: 20ba2bafdffed9b2d8fb9ce9e10cc62e62748bc7
https://github.com/qemu/qemu/commit/20ba2bafdffed9b2d8fb9ce9e10cc62e62748bc7
Author: Peter Maydell <[email protected]>
Date: 2024-11-01 (Fri, 01 Nov 2024)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/cirrus.yml
R .gitlab-ci.d/cirrus/macos-15.vars
M .gitlab-ci.d/crossbuilds.yml
M .travis.yml
M MAINTAINERS
A configs/devices/sh4eb-softmmu/default.mak
A configs/targets/sh4eb-softmmu.mak
M hw/m68k/next-cube.c
M hw/s390x/Kconfig
M qapi/machine.json
M tests/avocado/boot_linux_console.py
R tests/avocado/riscv_opensbi.py
R tests/avocado/tcg_plugins.py
M tests/functional/meson.build
M tests/functional/qemu_test/asset.py
M tests/functional/qemu_test/tuxruntest.py
M tests/functional/qemu_test/utils.py
A tests/functional/test_aarch64_tcg_plugins.py
A tests/functional/test_arm_bpim2u.py
A tests/functional/test_arm_orangepi.py
M tests/functional/test_ppc64_tuxrun.py
A tests/functional/test_riscv_opensbi.py
A tests/functional/test_sh4eb_r2d.py
M tests/lcitool/refresh
M tests/qemu-iotests/testenv.py
M tests/qtest/endianness-test.c
M tests/qtest/machine-none-test.c
M tests/qtest/meson.build
M tests/vm/openbsd
Log Message:
-----------
Merge tag 'pull-request-2024-10-31' of https://gitlab.com/thuth/qemu into
staging
* Remove the redundant macOS-15 CI job
* Various fixes, improvements and additions for the functional test suite
* Restore the sh4eb target
* Fix the OpenBSD VM test
* Re-enable the pci-bridge device on s390x
* Minor clean-ups / fixes for the next-cube machine
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# gpg: Signature made Thu 31 Oct 2024 17:44:39 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "[email protected]"
# gpg: Good signature from "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2024-10-31' of https://gitlab.com/thuth/qemu:
tests/functional: Convert the riscv_opensbi avocado test into a standalone
test
tests/functional: Convert the OrangePi tests to the functional framework
tests/functional: Convert BananaPi tests to the functional framework
tests/functional: Convert the tcg_plugins test
next-cube: remove cpu parameter from next_scsi_init()
next-cube: fix up compilation when DEBUG_NEXT is enabled
hw/s390x: Re-enable the pci-bridge device on s390x
tests/functional: Fix the s390x and ppc64 tuxrun tests
tests/vm/openbsd: Remove the "Time appears wrong" workaround
tests/functional: Add a test for sh4eb
Revert "Remove the unused sh4eb target"
tests/functional: make cached asset files read-only
tests/functional: make tuxrun disk images writable
.gitlab-ci.d/cirrus: Remove the macos-15 job
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/92ec78051903...20ba2bafdffe
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