Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: c3ec57e495b032047ddfef2075792340c407532a
https://github.com/qemu/qemu/commit/c3ec57e495b032047ddfef2075792340c407532a
Author: Mattias Nissler <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M include/exec/memory.h
M include/hw/pci/pci_device.h
Log Message:
-----------
softmmu: Expand comments describing max_bounce_buffer_size
Clarify how the parameter gets configured and how it is used when
servicing DMA mapping requests targeting indirect memory regions.
Signed-off-by: Mattias Nissler <[email protected]>
Message-Id: <[email protected]>
Acked-by: Peter Xu <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: b87ea798eb83693286cb2db6606280431e02628d
https://github.com/qemu/qemu/commit/b87ea798eb83693286cb2db6606280431e02628d
Author: luzhixing12345 <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: fix vhost-user protocol doc
Some editorial tweaks to the doc:
Add a ref link to Memory region description and Multiple Memory region
description.
Descriptions about memory regions are merged into one line.
Add extra type(64 bits) to Log description structure fields
Fix ’s to 's
Signed-off-by: luzhixing12345 <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 16c687d84574a1139a6475c33e3b9191f7932ac0
https://github.com/qemu/qemu/commit/16c687d84574a1139a6475c33e3b9191f7932ac0
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/acpi_generic_initiator.c
Log Message:
-----------
hw/acpi: Fix ordering of BDF in Generic Initiator PCI Device Handle.
The ordering in ACPI specification [1] has bus number in the lowest byte.
As ACPI tables are little endian this is the reverse of the ordering
used by PCI_BUILD_BDF(). As a minimal fix split the QEMU BDF up
into bus and devfn and write them as single bytes in the correct
order.
[1] ACPI Spec 6.3, Table 5.80
Fixes: 0a5b5acdf2d8 ("hw/acpi: Implement the SRAT GI affinity structure")
Reviewed-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: dc55a90e295e05b6246b0b152a854612467e417f
https://github.com/qemu/qemu/commit/dc55a90e295e05b6246b0b152a854612467e417f
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/acpi_generic_initiator.c
Log Message:
-----------
hw/acpi/GI: Fix trivial parameter alignment issue.
Before making additional modification, tidy up this misleading indentation.
Reviewed-by: Ankit Agrawal <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: d8a4b4c3b4dd258c5f5f6237473349d377ea7fc9
https://github.com/qemu/qemu/commit/d8a4b4c3b4dd258c5f5f6237473349d377ea7fc9
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/acpi_generic_initiator.c
M hw/acpi/aml-build.c
M include/hw/acpi/acpi_generic_initiator.h
M include/hw/acpi/aml-build.h
Log Message:
-----------
hw/acpi: Move AML building code for Generic Initiators to aml_build.c
Rather than attempting to create a generic function with mess of the two
different device handle types, use a PCI handle specific variant. If the
ACPI handle form is needed then that can be introduced alongside this
with little duplicated code.
Drop the PCIDeviceHandle in favor of just passing the bus, devfn
and segment directly. devfn kept as a single byte because ARI means
that in this case it is just an 8 bit function number.
Suggested-by: Igor Mammedov <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]/
Tested-by: "Huang, Ying" <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: a20b6c8f0b279edf370bc20b7845f87c36d03f7a
https://github.com/qemu/qemu/commit/a20b6c8f0b279edf370bc20b7845f87c36d03f7a
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/acpi_generic_initiator.c
Log Message:
-----------
hw/acpi: Rename build_all_acpi_generic_initiators() to
build_acpi_generic_initiator()
Igor noted that this function only builds one instance, so was rather
misleadingly named. Fix that.
Suggested-by: Igor Mammedov <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: df9ac7254fd943c834f9666969b0852b50e91692
https://github.com/qemu/qemu/commit/df9ac7254fd943c834f9666969b0852b50e91692
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/acpi_generic_initiator.c
M hw/pci/pci.c
Log Message:
-----------
hw/pci: Add a busnr property to pci_props and use for acpi/gi
Using a property allows us to hide the internal details of the PCI device
from the code to build a SRAT Generic Initiator Affinity Structure with
PCI Device Handle.
Suggested-by: Igor Mammedov <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: f74e78220dbfec557922eb6e8ec0a78d08743e02
https://github.com/qemu/qemu/commit/f74e78220dbfec557922eb6e8ec0a78d08743e02
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
R hw/acpi/acpi_generic_initiator.c
M hw/acpi/meson.build
M hw/acpi/pci.c
M hw/arm/virt-acpi-build.c
M hw/i386/acpi-build.c
R include/hw/acpi/acpi_generic_initiator.h
M include/hw/acpi/pci.h
Log Message:
-----------
acpi/pci: Move Generic Initiator object handling into acpi/pci.*
Whilst ACPI SRAT Generic Initiator Afinity Structures are able to refer to
both PCI and ACPI Device Handles, the QEMU implementation only implements
the PCI Device Handle case. For now move the code into the existing
hw/acpi/pci.c file and header. If support for ACPI Device Handles is
added in the future, perhaps this will be moved again.
Also push the struct AcpiGenericInitiator down into the c file as not
used outside pci.c.
Suggested-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 97b9cb066e5f10845b4bc4d2ec657deb1e73f910
https://github.com/qemu/qemu/commit/97b9cb066e5f10845b4bc4d2ec657deb1e73f910
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
Log Message:
-----------
hw/pci-bridge: Add acpi_uid property to TYPE_PXB_BUS
Enable ACPI table creation for PCI Expander Bridges to be independent
of PCI internals. Note that the UID is currently the PCI bus number.
This is motivated by the forthcoming ACPI Generic Port SRAT entries
which can be made completely independent of PCI internals.
Suggested-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: dc907b5cac14ef06f59963d697e81ff2516b9b3f
https://github.com/qemu/qemu/commit/dc907b5cac14ef06f59963d697e81ff2516b9b3f
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi: Use TYPE_PXB_BUS property acpi_uid for DSDT
Rather than relying on PCI internals, use the new acpi_property
to obtain the ACPI _UID values. These are still the same
as the PCI Bus numbers so no functional change.
Suggested-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 43eb5e1f73f1b943d952d9776681a51f05ca7aa8
https://github.com/qemu/qemu/commit/43eb5e1f73f1b943d952d9776681a51f05ca7aa8
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-host/gpex-acpi.c
Log Message:
-----------
hw/pci-host/gpex-acpi: Use acpi_uid property.
Reduce the direct use of PCI internals inside ACPI table creation.
Suggested-by: Igor Mammedov <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Reviewed-by: Igor Mammedov <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: a82fe82916432091ca6fcbd7f357cccf35f6e80d
https://github.com/qemu/qemu/commit/a82fe82916432091ca6fcbd7f357cccf35f6e80d
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/aml-build.c
M hw/acpi/pci.c
M hw/arm/virt-acpi-build.c
M hw/i386/acpi-build.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/acpi/aml-build.h
M include/hw/acpi/pci.h
M include/hw/pci/pci_bridge.h
M qapi/qom.json
Log Message:
-----------
hw/acpi: Generic Port Affinity Structure support
These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators. Here we add these ports such that they may
be targets of hmat_lb records to describe the latency and
bandwidth from host side initiators to the port. A discoverable
mechanism such as UEFI CDAT read from CXL devices and switches
is used to discover the remainder of the path, and the OS can build
up full latency and bandwidth numbers as need for work and data
placement decisions.
Acked-by: Markus Armbruster <[email protected]>
Tested-by: "Huang, Ying" <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: cf2181aef23e7f145e8fe7b8395694d32b115ae5
https://github.com/qemu/qemu/commit/cf2181aef23e7f145e8fe7b8395694d32b115ae5
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/aml-build.c
M hw/acpi/pci.c
M include/hw/acpi/aml-build.h
Log Message:
-----------
hw/acpi: Make storage of node id uint32_t to reduce fragility
>From review of generic port introduction.
The value is handled as a uint32_t so store it in that type.
The value cannot in reality exceed MAX_NODES which is currently
128 but if the types are matched there is no need to rely on that
restriction.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: df37d496981344c24746be3553d7f6d8a0a9b1b9
https://github.com/qemu/qemu/commit/df37d496981344c24746be3553d7f6d8a0a9b1b9
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/pci.c
Log Message:
-----------
hw/acpi: Generic Initiator - add missing object class property descriptions.
>From review of the Generic Ports support.
These properties had no description set so add one.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 1478b5609022ed4331bff83d06cefed983df82ac
https://github.com/qemu/qemu/commit/1478b5609022ed4331bff83d06cefed983df82ac
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-bridge/cxl_root_port.c
Log Message:
-----------
hw/pci-bridge/cxl_root_port: Provide x-speed and x-width properties.
Approach copied from gen_pcie_root_port.c
Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting
it's maximum values. The actual value after 'training' will depend on the
downstream device configuration.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Fan Ni <[email protected]>
Commit: 845f94de78cb6c063234176ff7c0ac8e430d19fe
https://github.com/qemu/qemu/commit/845f94de78cb6c063234176ff7c0ac8e430d19fe
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-bridge/cxl_downstream.c
Log Message:
-----------
hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.
Copied from gen_pcie_root_port.c
Drop the previous code that ensured a valid value in s->width, s->speed
as now a default is provided so this will always be set.
Note this changes the default settings but it is unlikely to have a negative
effect on software as will only affect ports with now downstream device.
All other ports will use the settings from that device.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 6d1bda91337dcd0e7bf78da6f6b15af497966052
https://github.com/qemu/qemu/commit/6d1bda91337dcd0e7bf78da6f6b15af497966052
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci/pcie.c
Log Message:
-----------
hw/pcie: Factor out PCI Express link register filling common to EP.
Whilst not all link related registers are common between RP / Switch DSP
and EP / Switch USP many of them are. Factor that group out to save
on duplication when adding EP / Swtich USP configurability.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: ea3f0ebc1a3ba380e682ea8aad38f8e8cbc0d6f7
https://github.com/qemu/qemu/commit/ea3f0ebc1a3ba380e682ea8aad38f8e8cbc0d6f7
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci/pcie.c
M include/hw/pci/pcie.h
Log Message:
-----------
hw/pcie: Provide a utility function for control of EP / SW USP link
Whilst similar to existing PCIESlot link configuration a few registers
need to be set differently so that the downstream device presents
a 'configured' state that is then used to 'train' the upstream port
on the link. Basically that means setting the status register to
reflect it succeeding in training up to target settings.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 14bd0f3865489d537a93b7c80617622473f224e4
https://github.com/qemu/qemu/commit/14bd0f3865489d537a93b7c80617622473f224e4
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/mem/cxl-type3: Add properties to control link speed and width
To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure. Provide x-speed and x-link properties for this.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: fa19fe4e3a61765ff60914ee00fc1e7a6a38dba9
https://github.com/qemu/qemu/commit/fa19fe4e3a61765ff60914ee00fc1e7a6a38dba9
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-bridge/cxl_upstream.c
M include/hw/pci-bridge/cxl_upstream_port.h
Log Message:
-----------
hw/pci-bridge/cxl-upstream: Add properties to control link speed and width
To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure. Provide x-speed and x-link properties for this.
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 9e4cc917e0be9c757d834a0e40c66def1fed5adc
https://github.com/qemu/qemu/commit/9e4cc917e0be9c757d834a0e40c66def1fed5adc
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M system/qdev-monitor.c
Log Message:
-----------
qdev-monitor: add option to report GenericError from find_device_state
Here we just prepare for the following patch, making possible to report
GenericError as recommended.
This patch doesn't aim to prevent further use of DeviceNotFound by
future interfaces:
- find_device_state() is used in blk_by_qdev_id() and qmp_get_blk()
functions, which may lead to spread of DeviceNotFound anyway
- also, nothing prevent simply copy-pasting find_device_state() calls
with false argument
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Acked-by: Raphael Norwitz <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 4dfa12731439c4a3cbfd9d1767acddfbf79549fd
https://github.com/qemu/qemu/commit/4dfa12731439c4a3cbfd9d1767acddfbf79549fd
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/block/vhost-user-blk.c
Log Message:
-----------
vhost-user-blk: split vhost_user_blk_sync_config()
Split vhost_user_blk_sync_config() out from
vhost_user_blk_handle_config_change(), to be reused in the following
commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Acked-by: Raphael Norwitz <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Stefano Garzarella <[email protected]>
Commit: 3f98408e2e4fb1792102aed2cd5425aa0e34cc9c
https://github.com/qemu/qemu/commit/3f98408e2e4fb1792102aed2cd5425aa0e34cc9c
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/virtio/virtio-pci.c
M include/hw/qdev-core.h
M qapi/qdev.json
M system/qdev-monitor.c
Log Message:
-----------
qapi: introduce device-sync-config
Add command to sync config from vhost-user backend to the device. It
may be helpful when VHOST_USER_SLAVE_CONFIG_CHANGE_MSG failed or not
triggered interrupt to the guest or just not available (not supported
by vhost-user server).
Command result is racy if allow it during migration. Let's not allow
that.
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Acked-by: Raphael Norwitz <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: feb58e3b261db503ade94c5f43ccedeee4eac41f
https://github.com/qemu/qemu/commit/feb58e3b261db503ade94c5f43ccedeee4eac41f
Author: Michael S. Tsirkin <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/data/acpi/disassemle-aml.sh
Log Message:
-----------
acpi/disassemle-aml.sh: fix up after dir reorg
We moved expected files around, fix up the disassembler script.
Fixes: 7c08eefcaf ("tests/data/acpi: Move x86 ACPI tables under x86/${machine}
path")
Fixes: 7434f90467 ("tests/data/acpi/virt: Move ARM64 ACPI tables under
aarch64/${machine} path")
Cc: "Sunil V L" <[email protected]>
Message-ID:
<ce456091058734b7f765617ac5dfeebcb366d4a9.1730729695.git....@redhat.com>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Acked-by: Igor Mammedov <[email protected]>
Commit: d944497b5519cdefe2d38cf68317b93e14dd388a
https://github.com/qemu/qemu/commit/d944497b5519cdefe2d38cf68317b93e14dd388a
Author: Ricardo Ribalda <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: pc: allow DSDT acpi table changes
Signed-off-by: Ricardo Ribalda <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Acked-by: Igor Mammedov <[email protected]>
Commit: 7916bb54319a56be5c5eca0c890a4d2aa22b9bef
https://github.com/qemu/qemu/commit/7916bb54319a56be5c5eca0c890a4d2aa22b9bef
Author: Ricardo Ribalda <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: return a non-var package from _PRT()
Windows XP seems to have issues when _PRT() returns a variable package.
We know in advance the size, so we can return a fixed package instead.
https://lore.kernel.org/qemu-devel/[email protected]/T/#m541190c942676bccf7a7f7fbcb450d94a4e2da53
Reviewed-by: Igor Mammedov <[email protected]>
Reported-by: Mark Cave-Ayland <[email protected]>
Fixes: 99cb2c6c7b ("hw/i386/acpi-build: Return a pre-computed _PRT table")
Closes:
https://lore.kernel.org/all/[email protected]/
Signed-off-by: Ricardo Ribalda <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 9848a76c0b56172a370640744e99fe78fea4d4c0
https://github.com/qemu/qemu/commit/9848a76c0b56172a370640744e99fe78fea4d4c0
Author: Ricardo Ribalda <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.hpbrroot
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.viot
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: pc: update golden masters for DSDT
Note: since all we did is replace VarPackageOp with PackageOP,
and both are represented by Package() in ASL, the AML is
different but ASL is the same.
Signed-off-by: Ricardo Ribalda <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Acked-by: Igor Mammedov <[email protected]>
Commit: 2e6f051cfc58e69dcb392cd245d8f01b0c2e963f
https://github.com/qemu/qemu/commit/2e6f051cfc58e69dcb392cd245d8f01b0c2e963f
Author: Suravee Suthikulpanit <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/acpi-build.c
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
Log Message:
-----------
amd_iommu: Rename variable mmio to mr_mmio
Rename the MMIO memory region variable 'mmio' to 'mr_mmio'
so to correctly name align with struct AMDVIState::variable type.
No functional change intended.
Reviewed-by: Alejandro Jimenez <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Santosh Shukla <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: c1f46999ef506d9854534560a94d02cf3cf9edd1
https://github.com/qemu/qemu/commit/c1f46999ef506d9854534560a94d02cf3cf9edd1
Author: Suravee Suthikulpanit <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
Log Message:
-----------
amd_iommu: Add support for pass though mode
Introduce 'nodma' shared memory region to support PT mode
so that for each device, we only create an alias to shared memory
region when DMA-remapping is disabled.
Reviewed-by: Alejandro Jimenez <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Santosh Shukla <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 9fc9dbac61ddde7d8df37e84c8e02cec249d3222
https://github.com/qemu/qemu/commit/9fc9dbac61ddde7d8df37e84c8e02cec249d3222
Author: Suravee Suthikulpanit <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
Log Message:
-----------
amd_iommu: Use shared memory region for Interrupt Remapping
Use shared memory region for interrupt remapping which can be
aliased by all devices.
Reviewed-by: Alejandro Jimenez <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Santosh Shukla <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: f84aad4d718b83d2a4d90485992e5421430032e1
https://github.com/qemu/qemu/commit/f84aad4d718b83d2a4d90485992e5421430032e1
Author: Suravee Suthikulpanit <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
amd_iommu: Send notification when invalidate interrupt entry cache
In order to support AMD IOMMU interrupt remapping emulation with PCI
pass-through devices, QEMU needs to notify VFIO when guest IOMMU driver
updates and invalidate the guest interrupt remapping table (IRT), and
communicate information so that the host IOMMU driver can update
the shadowed interrupt remapping table in the host IOMMU.
Therefore, send notification when guest IOMMU emulates the IRT
invalidation commands.
Reviewed-by: Alejandro Jimenez <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Santosh Shukla <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: b12cb3819baf6d9ee8140d4dd6d36fa829e2c6d9
https://github.com/qemu/qemu/commit/b12cb3819baf6d9ee8140d4dd6d36fa829e2c6d9
Author: Suravee Suthikulpanit <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
amd_iommu: Check APIC ID > 255 for XTSup
The XTSup mode enables x2APIC support for AMD IOMMU, which is needed
to support vcpu w/ APIC ID > 255.
Reviewed-by: Alejandro Jimenez <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Santosh Shukla <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 55fa4be6f76a3e1b1caa33a8f0ab4dc217d32e49
https://github.com/qemu/qemu/commit/55fa4be6f76a3e1b1caa33a8f0ab4dc217d32e49
Author: Gao Shiyuan <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci/pci_bridge.c
M hw/virtio/virtio-pci.c
M include/hw/pci/pci_bridge.h
M include/hw/virtio/virtio-pci.h
A tests/qtest/fuzz-virtio-balloon-test.c
M tests/qtest/meson.build
Log Message:
-----------
virtio-pci: fix memory_region_find for VirtIOPCIRegion's MR
As shown below, if a virtio PCI device is attached under a pci-bridge, the MR
of VirtIOPCIRegion does not belong to any address space. So memory_region_find
cannot be used to search for this MR.
Introduce the virtio-pci and pci_bridge address spaces to solve this problem.
Before:
memory-region: pci_bridge_pci
0000000000000000-ffffffffffffffff (prio 0, i/o): pci_bridge_pci
00000000fe840000-00000000fe840fff (prio 1, i/o): virtio-net-pci-msix
00000000fe840000-00000000fe84003f (prio 0, i/o): msix-table
00000000fe840800-00000000fe840807 (prio 0, i/o): msix-pba
0000380000000000-0000380000003fff (prio 1, i/o): virtio-pci
0000380000000000-0000380000000fff (prio 0, i/o):
virtio-pci-common-virtio-net
0000380000001000-0000380000001fff (prio 0, i/o): virtio-pci-isr-virtio-net
0000380000002000-0000380000002fff (prio 0, i/o):
virtio-pci-device-virtio-net
0000380000003000-0000380000003fff (prio 0, i/o):
virtio-pci-notify-virtio-net
After:
address-space: virtio-pci-cfg-mem-as
0000380000000000-0000380000003fff (prio 1, i/o): virtio-pci
0000380000000000-0000380000000fff (prio 0, i/o):
virtio-pci-common-virtio-net
0000380000001000-0000380000001fff (prio 0, i/o): virtio-pci-isr-virtio-net
0000380000002000-0000380000002fff (prio 0, i/o):
virtio-pci-device-virtio-net
0000380000003000-0000380000003fff (prio 0, i/o):
virtio-pci-notify-virtio-net
address-space: pci_bridge_pci_mem
0000000000000000-ffffffffffffffff (prio 0, i/o): pci_bridge_pci
00000000fe840000-00000000fe840fff (prio 1, i/o): virtio-net-pci-msix
00000000fe840000-00000000fe84003f (prio 0, i/o): msix-table
00000000fe840800-00000000fe840807 (prio 0, i/o): msix-pba
0000380000000000-0000380000003fff (prio 1, i/o): virtio-pci
0000380000000000-0000380000000fff (prio 0, i/o):
virtio-pci-common-virtio-net
0000380000001000-0000380000001fff (prio 0, i/o): virtio-pci-isr-virtio-net
0000380000002000-0000380000002fff (prio 0, i/o):
virtio-pci-device-virtio-net
0000380000003000-0000380000003fff (prio 0, i/o):
virtio-pci-notify-virtio-net
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2576
Fixes: ffa8a3e3b2e6 ("virtio-pci: Add lookup subregion of VirtIOPCIRegion MR")
Co-developed-by: Zuo Boqun <[email protected]>
Signed-off-by: Zuo Boqun <[email protected]>
Co-developed-by: Wang Liang <[email protected]>
Signed-off-by: Wang Liang <[email protected]>
Signed-off-by: Gao Shiyuan <[email protected]>
Message-Id: <[email protected]>
Tested-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 963b02764537c66af88b82bd297c375b147e0756
https://github.com/qemu/qemu/commit/963b02764537c66af88b82bd297c375b147e0756
Author: yaozhenguo <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
virtio/vhost-user: fix qemu abort when hotunplug vhost-user-net device
During the hot-unplugging of vhost-user-net type network cards,
the vhost_user_cleanup function may add the same rcu node to
the rcu linked list. The function call in this case is as follows:
vhost_user_cleanup
->vhost_user_host_notifier_remove
->call_rcu(n, vhost_user_host_notifier_free, rcu);
->g_free_rcu(n, rcu);
When this happens, QEMU will abort in try_dequeue:
if (head == &dummy && qatomic_mb_read(&tail) == &dummy.next) {
abort();
}
backtrace is as follows:
0 __pthread_kill_implementation () at /usr/lib64/libc.so.6
1 raise () at /usr/lib64/libc.so.6
2 abort () at /usr/lib64/libc.so.6
3 try_dequeue () at ../util/rcu.c:235
4 call_rcu_thread (0) at ../util/rcu.c:288
5 qemu_thread_start (0) at ../util/qemu-thread-posix.c:541
6 start_thread () at /usr/lib64/libc.so.6
7 clone3 () at /usr/lib64/libc.so.6
The reason for the abort is that adding two identical nodes to
the rcu linked list will cause the rcu linked list to become a ring,
but when the dummy node is added after the two identical nodes,
the ring is opened. But only one node is added to list with
rcu_call_count added twice. This will cause rcu try_dequeue abort.
This happens when n->addr != 0. In some scenarios, this does happen.
For example, this situation will occur when using a 32-queue DPU
vhost-user-net type network card for hot-unplug testing, because
VhostUserHostNotifier->addr will be cleared during the processing of
VHOST_USER_BACKEND_VRING_HOST_NOTIFIER_MSG. However,it is asynchronous,
so we cannot guarantee that VhostUserHostNotifier->addr is zero in
vhost_user_cleanup. Therefore, it is necessary to merge g_free_rcu
and vhost_user_host_notifier_free into one rcu node.
Fixes: 503e355465 ("virtio/vhost-user: dynamically assign
VhostUserHostNotifiers")
Signed-off-by: yaozhenguo <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Stefano Garzarella <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: df66b85f357f9669457906ece865d6183cf12580
https://github.com/qemu/qemu/commit/df66b85f357f9669457906ece865d6183cf12580
Author: Dmitry Frolov <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Fix uint32 overflow cxl-mailbox-utils.c
The sum offset + length may overflow uint32. Since this sum is
compared with uint64_t return value of get_lsa_size(), it makes
sense to choose uint64_t type for offset and length.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 3ebe676a3463 ("hw/cxl/device: Implement get/set Label Storage Area
(LSA)")
Signed-off-by: Dmitry Frolov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 8352756ffa72668773d6904bc76dfc0bf2619e5a
https://github.com/qemu/qemu/commit/8352756ffa72668773d6904bc76dfc0bf2619e5a
Author: Ajay Joshi <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Fix background completion percentage calculation
The current completion percentage calculation does not account for the
relative time since the start of the background activity, this leads to
showing incorrect start percentage vs what has actually been completed.
This patch calculates the percentage based on the actual elapsed time since
the start of the operation.
Fixes: 221d2cfbdb53 ("hw/cxl/mbox: Add support for background operations")
Signed-off-by: Ajay Joshi <[email protected]>
Reviewed-by: Davidlohr Bueso <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 5eabca7ec0a92032c7dd5188f1708344c225a385
https://github.com/qemu/qemu/commit/5eabca7ec0a92032c7dd5188f1708344c225a385
Author: Yao Xingtao <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
mem/cxl_type3: Fix overlapping region validation error
When injecting a new poisoned region through qmp_cxl_inject_poison(),
the newly injected region should not overlap with existing poisoned
regions.
The current validation method does not consider the following
overlapping region:
┌───┬───────┬───┐
│a │ b(a) │a │
└───┴───────┴───┘
(a is a newly added region, b is an existing region, and b is a
subregion of a)
Fixes: 9547754f40ee ("hw/cxl: QMP based poison injection support")
Signed-off-by: Yao Xingtao <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 80ee960f8d646505385bce8ed143a9bb8ea36d1d
https://github.com/qemu/qemu/commit/80ee960f8d646505385bce8ed143a9bb8ea36d1d
Author: Fan Ni <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/mem/cxl_type3: Fix More flag setting for dynamic capacity event records
Per cxl spec r3.1, for multiple dynamic capacity event records grouped via
the More flag, the last record in the sequence should clear the More flag.
Before the change, the More flag of the event record is cleared before
the loop of inserting records into the event log, which will leave the flag
always set once it is set in the loop.
Fixes: d0b9b28a5b9f ("hw/cxl/events: Add qmp interfaces to add/release dynamic
capacity extents")
Signed-off-by: Fan Ni <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: d1853190db5c59ad5b0537a2ac59c8d4494cbd98
https://github.com/qemu/qemu/commit/d1853190db5c59ad5b0537a2ac59c8d4494cbd98
Author: Shiju Jose <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
ECS log capabilities field in following ECS tables, which is common for all
memory media FRUs in a CXL device.
Fix struct CXLMemECSReadAttrs and struct CXLMemECSWriteAttrs to make
log entry type field common.
Fixes: 2d41ce38fb9a ("hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control
feature")
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: d1978226c81b0e9b3d6a7779cf92cbfe9f4a10e8
https://github.com/qemu/qemu/commit/d1978226c81b0e9b3d6a7779cf92cbfe9f4a10e8
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Fix indent of structure member
Add missing 4 spaces of indent to structure element.
Reported-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: d4d5212c541f57c339a592bcf1b38bf325940bfd
https://github.com/qemu/qemu/commit/d4d5212c541f57c339a592bcf1b38bf325940bfd
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
Log Message:
-----------
hw/pci-bridge: Make pxb_dev_realize_common() return if it succeeded
For the CXL PXB there is additional code after pxb_dev_realize_common()
is called. If that realize failed (e.g. due to an out of range numa_node)
we will get a segfault. Return a bool so the caller can check if the
pxb_dev_realize_common() succeeded or not without having to poke around
in the errp.
Fixes: 4f8db8711cbd ("hw/pxb: Allow creation of a CXL PXB (host bridge)")
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: eea5aeef84e1b74f515b474d3a86377701f93750
https://github.com/qemu/qemu/commit/eea5aeef84e1b74f515b474d3a86377701f93750
Author: Albert Esteve <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: fix shared object return values
VHOST_USER_BACKEND_SHARED_OBJECT_ADD and
VHOST_USER_BACKEND_SHARED_OBJECT_REMOVE state
in the spec that they return 0 for successful
operations, non-zero otherwise. However,
implementation relies on the return types
of the virtio-dmabuf library, with opposite
semantics (true if everything is correct,
false otherwise). Therefore, current
implementation violates the specification.
Revert the logic so that the implementation
of the vhost-user handling methods matches
the specification.
Fixes: 043e127a126bb3ceb5fc753deee27d261fd0c5ce
Fixes: 160947666276c5b7f6bca4d746bcac2966635d79
Reviewed-by: Stefano Garzarella <[email protected]>
Signed-off-by: Albert Esteve <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 6ce12bd29777d41afef859652eaa62b5c964d3f7
https://github.com/qemu/qemu/commit/6ce12bd29777d41afef859652eaa62b5c964d3f7
Author: Zhenzhong Duan <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/pc.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM)
field
VT-d spec removed Transient Mapping (TM) field from second-level page-tables
and treat the field as Reserved(0) since revision 3.2.
Changing the field as reserved(0) will break backward compatibility, so
introduce a property "stale-tm" to allow user to control the setting.
Use pc_compat_9_1 to handle the compatibility for machines before 9.2 which
allow guest to set the field. Starting from 9.2, this field is reserved(0)
by default to match spec. Of course, user can force it on command line.
This doesn't impact function of vIOMMU as there was no logic to emulate
Transient Mapping.
Suggested-by: Yi Liu <[email protected]>
Suggested-by: Jason Wang <[email protected]>
Signed-off-by: Zhenzhong Duan <[email protected]>
Acked-by: Jason Wang <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Clément Mathieu--Drif<[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 449dca6ac93afbed1af00b6a29c9729f6cb18c35
https://github.com/qemu/qemu/commit/449dca6ac93afbed1af00b6a29c9729f6cb18c35
Author: Marcin Juszkiewicz <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/core/machine.c
M hw/pci/pci.c
M hw/pci/pcie.c
M include/hw/pci/pci.h
Log Message:
-----------
pcie: enable Extended tag field support
>From what I read PCI has 32 transactions, PCI Express devices can handle
256 with Extended tag enabled (spec mentions also larger values but I
lack PCIe knowledge).
QEMU leaves 'Extended tag field' with 0 as value:
Capabilities: [e0] Express (v1) Root Complex Integrated Endpoint, IntMsgNum 0
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE+ FLReset- TEE-IO-
SBSA ACS has test 824 which checks for PCIe device capabilities. BSA
specification [1] (SBSA is on top of BSA) in section F.3.2 lists
expected values for Device Capabilities Register:
Device Capabilities Register Requirement
Role based error reporting RCEC and RCiEP: Hardwired to 1
Endpoint L0s acceptable latency RCEC and RCiEP: Hardwired to 0
L1 acceptable latency RCEC and RCiEP: Hardwired to 0
Captured slot power limit scale RCEC and RCiEP: Hardwired to 0
Captured slot power limit value RCEC and RCiEP: Hardwired to 0
Max payload size value must be compliant with PCIe spec
Phantom functions RCEC and RCiEP: Recommendation is to
hardwire this bit to 0.
Extended tag field Hardwired to 1
1. https://developer.arm.com/documentation/den0094/c/
This change enables Extended tag field. All versioned platforms should
have it disabled for older versions (tested with Arm/virt).
Signed-off-by: Marcin Juszkiewicz <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 0564019bf1d9dd76ee7d212c26cf40e73eb3a00c
https://github.com/qemu/qemu/commit/0564019bf1d9dd76ee7d212c26cf40e73eb3a00c
Author: Fan Ni <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
cxl/cxl-mailbox-utils: Fix size check for cmd_firmware_update_get_info
In the function cmd_firmware_update_get_info for handling Get FW info
command (0x0200h), the vmem, pmem and DC capacity size check were
incorrect. The size should be aligned to 256MiB, not smaller than
256MiB.
Signed-off-by: Fan Ni <[email protected]>
Reviewed-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 802671c37a6ab4de116866883841bcc8b2318124
https://github.com/qemu/qemu/commit/802671c37a6ab4de116866883841bcc8b2318124
Author: Fan Ni <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/cxl-mailbox-util: Fix output buffer index update when retrieving DC
extents
In the function of retrieving DC extents (cmd_dcd_get_dyn_cap_ext_list),
the output buffer index was not correctly updated while iterating the
extent list on the device, leaving the extents returned incorrect except for
the first one.
Fixes: 1c9221f19e62 ("hw/mem/cxl_type3: Add DC extent list representative and
get DC extent list mailbox support")
Signed-off-by: Fan Ni <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 7edbbff5ee85dd28699c5acd6ea2f2c2e41c37d2
https://github.com/qemu/qemu/commit/7edbbff5ee85dd28699c5acd6ea2f2c2e41c37d2
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check size of input data to dynamic capacity mailbox commands
cxl_cmd_dcd_release_dyn_cap() and cmd_dcd_add_dyn_cap_rsp() are missing
input message size checks. These must be done in the individual
commands when the command has a variable length input payload.
A buggy or malicious guest might send undersized messages via the mailbox.
As that size is used to take a copy of the mailbox content, each command
must check there is sufficient data. In this case the first check is that
there is enough data to read how many extents there are, and the second
that there is enough for those elements to be accessed.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 91a743bd021a262af61c79cc35f0b634b2fcf3ad
https://github.com/qemu/qemu/commit/91a743bd021a262af61c79cc35f0b634b2fcf3ad
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check input includes at least the header in cmd_features_set_feature()
A buggy guest might write an insufficiently large message.
Check the header is present. Whilst zero data after the header is very
odd it will just result in failure to copy any data.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: f4a12ba66bebfe200d7f56015c1cd5af321ab152
https://github.com/qemu/qemu/commit/f4a12ba66bebfe200d7f56015c1cd5af321ab152
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check input length is large enough in cmd_events_clear_records()
Buggy software might write a message that is too short for
either the header, or the header + the event data that is specified
in the header. This may result in accesses beyond the range of the
message allocated as a duplicate of the incoming message buffer.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: a3995360aeec62902f045142840c1fd334e9725f
https://github.com/qemu/qemu/commit/a3995360aeec62902f045142840c1fd334e9725f
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check enough data in cmd_firmware_update_transfer()
Buggy guest can write a message that advertises more data that
is provided. As QEMU internally duplicates the reported message
size, this may result in an out of bounds access.
Add sanity checks on the size to avoid this.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: f9f0fa2438c6934aa76b06e9a6cef283176ceb8d
https://github.com/qemu/qemu/commit/f9f0fa2438c6934aa76b06e9a6cef283176ceb8d
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check the length of data requested fits in get_log()
Checking offset + length is of no relevance when verifying the CEL
data will fit in the mailbox payload. Only the length is is relevant.
Note that this removes a potential overflow.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: a3de73c2a835efc30851f9e810e0cd355e1cd0cf
https://github.com/qemu/qemu/commit/a3de73c2a835efc30851f9e810e0cd355e1cd0cf
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Avoid accesses beyond the end of cel_log.
Add a check that the requested offset + length does not go beyond the end
of the cel_log.
Whilst the cci->cel_log is large enough to include all possible CEL
entries, the guest might still ask for entries beyond the end of it.
Move the comment to this new check rather than before the check on the
type of log requested.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: c0f122419fbcd1e0bf2bc2a0a3ae6410bb2cda22
https://github.com/qemu/qemu/commit/c0f122419fbcd1e0bf2bc2a0a3ae6410bb2cda22
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Ensuring enough data to read parameters in cmd_tunnel_management_cmd()
If len_in is less than the minimum spec allowed value, then return
CXL_MBOX_INVALID_PAYLOAD_LENGTH
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: c1c4d6b38b13952b0a9e2d7393e1ccc70b2615a4
https://github.com/qemu/qemu/commit/c1c4d6b38b13952b0a9e2d7393e1ccc70b2615a4
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Check that writes do not go beyond end of target attributes
In cmd_features_set_feature() the an offset + data size schemed
is used to allow for large features. Ensure this does not write
beyond the end fo the buffers used to accumulate the full feature
attribute set.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 5300bdf5898dda5989215e183bccd555cc782b9a
https://github.com/qemu/qemu/commit/5300bdf5898dda5989215e183bccd555cc782b9a
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Ensure there is enough data for the header in cmd_ccls_set_lsa()
The properties of the requested set command cannot be established if
len_in is less than the size of the header.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 721c99aefcdb311bd41d20678d3935fd11454641
https://github.com/qemu/qemu/commit/721c99aefcdb311bd41d20678d3935fd11454641
Author: Jonathan Cameron <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Ensure there is enough data to read the input header in
cmd_get_physical_port_state()
If len_in is smaller than the header length then the accessing the
number of ports will result in an out of bounds access.
Add a check to avoid this.
Reported-by: Esifiel <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 26f2660bf7a3f0b6e9a939657ba656f4891ff46d
https://github.com/qemu/qemu/commit/26f2660bf7a3f0b6e9a939657ba656f4891ff46d
Author: Roque Arcudia Hernandez <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci: Add parenthesis to PCI_BUILD_BDF macro
The bus parameter in the macro PCI_BUILD_BDF is not surrounded by
parenthesis. This can create a compile error when warnings are
treated as errors or can potentially create runtime errors due to the
operator precedence.
For instance:
file.c:x:32: error: suggest parentheses around '-' inside '<<'
[-Werror=parentheses]
171 | uint16_t bdf = PCI_BUILD_BDF(a - b, sdev->devfn);
| ~~^~~
include/hw/pci/pci.h:19:41: note: in definition of macro
'PCI_BUILD_BDF'
19 | #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
| ^~~
cc1: all warnings being treated as errors
Signed-off-by: Roque Arcudia Hernandez <[email protected]>
Reviewed-by: Nabih Estefan <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 2d6cfbaf174b91dfa9a50065f7494634afb39c23
https://github.com/qemu/qemu/commit/2d6cfbaf174b91dfa9a50065f7494634afb39c23
Author: Salil Mehta <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/cpu.c
M include/hw/core/cpu.h
Log Message:
-----------
hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug
On most architectures, during vCPU hot-plug and hot-unplug actions, the
firmware or VMM/QEMU can update the OS on vCPU status by toggling the
ACPI method `_STA.Present` bit. However, certain CPU architectures
prohibit [1] modifications to a CPU’s `presence` status after the kernel
has booted.
This limitation [2][3] exists because many per-CPU components, such as
interrupt controllers and various per-CPU features tightly integrated
with CPUs, may not support reconfiguration once the kernel is
initialized. Often, these components cannot be powered down, as they may
belong to an `always-on` power domain. As a result, some architectures
require all CPUs to remain `_STA.Present` after system initialization.
Therefore, it is essential to mirror the exact QOM vCPU status through
ACPI for the Guest kernel. For this, we should determine—via
architecture-specific code[4]—whether vCPUs must always remain present
and whether the associated `AcpiCpuStatus::cpu` object should remain
valid, even following a vCPU hot-unplug operation.
References:
[1] Check comment 5 in the bugzilla entry
Link: https://bugzilla.tianocore.org/show_bug.cgi?id=4481#c5
[2] KVMForum 2023 Presentation: Challenges Revisited in Supporting Virt CPU
Hotplug on
architectures that don’t Support CPU Hotplug (like ARM64)
a. Kernel Link:
https://kvm-forum.qemu.org/2023/KVM-forum-cpu-hotplug_7OJ1YyJ.pdf
b. Qemu Link:
https://kvm-forum.qemu.org/2023/Challenges_Revisited_in_Supporting_Virt_CPU_Hotplug_-__ii0iNb3.pdf
[3] KVMForum 2020 Presentation: Challenges in Supporting Virtual CPU Hotplug on
SoC Based Systems (like ARM64)
Link: https://kvmforum2020.sched.com/event/eE4m
[4] Example implementation of architecture-specific CPU persistence hook
Link:
https://github.com/salil-mehta/qemu/commit/c0b416b11e5af6505e558866f0eb6c9f3709173e
Signed-off-by: Salil Mehta <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: e98411c2cbbac24ff49992a09226a2662726a031
https://github.com/qemu/qemu/commit/e98411c2cbbac24ff49992a09226a2662726a031
Author: Salil Mehta <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest: allow ACPI DSDT Table changes
list changed files in tests/qtest/bios-tables-test-allowed-diff.h
Reported-by: Zhao Liu <[email protected]>
Signed-off-by: Salil Mehta <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d
https://github.com/qemu/qemu/commit/bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d
Author: Salil Mehta <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/cpu.c
M include/hw/core/cpu.h
Log Message:
-----------
hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states
Reflect the QOM vCPUs ACPI CPU hotplug states in the `_STA.Present` and
and `_STA.Enabled` bits when the guest kernel evaluates the ACPI
`_STA` method during initialization, as well as when vCPUs are
hot-plugged or hot-unplugged. If the CPU is present then the its
`enabled` status can be fetched using architecture-specific code [1].
Reference:
[1] Example implementation of architecture-specific hook to fetch CPU
`enabled status
Link:
https://github.com/salil-mehta/qemu/commit/c0b416b11e5af6505e558866f0eb6c9f3709173e
Signed-off-by: Salil Mehta <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 4d62d15b11909e9af121577e707b88f2e4524371
https://github.com/qemu/qemu/commit/4d62d15b11909e9af121577e707b88f2e4524371
Author: Salil Mehta <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.hpbrroot
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DSDT
M tests/data/acpi/x86/q35/DSDT.acpierst
M tests/data/acpi/x86/q35/DSDT.acpihmat
M tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/x86/q35/DSDT.applesmc
M tests/data/acpi/x86/q35/DSDT.bridge
M tests/data/acpi/x86/q35/DSDT.core-count
M tests/data/acpi/x86/q35/DSDT.core-count2
M tests/data/acpi/x86/q35/DSDT.cphp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.dimmpxm
M tests/data/acpi/x86/q35/DSDT.ipmibt
M tests/data/acpi/x86/q35/DSDT.ipmismbus
M tests/data/acpi/x86/q35/DSDT.ivrs
M tests/data/acpi/x86/q35/DSDT.memhp
M tests/data/acpi/x86/q35/DSDT.mmio64
M tests/data/acpi/x86/q35/DSDT.multi-bridge
M tests/data/acpi/x86/q35/DSDT.noacpihp
M tests/data/acpi/x86/q35/DSDT.nohpet
M tests/data/acpi/x86/q35/DSDT.numamem
M tests/data/acpi/x86/q35/DSDT.pvpanic-isa
M tests/data/acpi/x86/q35/DSDT.thread-count
M tests/data/acpi/x86/q35/DSDT.thread-count2
M tests/data/acpi/x86/q35/DSDT.tis.tpm12
M tests/data/acpi/x86/q35/DSDT.tis.tpm2
M tests/data/acpi/x86/q35/DSDT.type4-count
M tests/data/acpi/x86/q35/DSDT.viot
M tests/data/acpi/x86/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35}
Update DSDT golden master files for x86/pc and x86/q35 platforms to
accommodate changes made in the architecture-agnostic CPU AML. These
updates notify the guest OS of vCPU hot-plug and hot-unplug status
using the ACPI `_STA.Enabled` bit.
The following is a diff of the changes in the .dsl file generated with
IASL:
@@ -1480,6 +1480,7 @@
CRMV, 1,
CEJ0, 1,
CEJF, 1,
+ CPRS, 1,
Offset (0x05),
CCMD, 8
}
@@ -1514,9 +1515,16 @@
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
- If ((\_SB.PCI0.PRES.CPEN == One))
- {
- Local0 = 0x0F
+ If ((\_SB.PCI0.PRES.CPRS == One))
+ {
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+ Else
+ {
+ Local0 = 0x0D
+ }
}
Release (\_SB.PCI0.PRES.CPLK)
Reported-by: Zhao Liu <[email protected]>
Signed-off-by: Salil Mehta <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 65fb66980d3a918ebe1e665cf6ae4ceb8dea2db1
https://github.com/qemu/qemu/commit/65fb66980d3a918ebe1e665cf6ae4ceb8dea2db1
Author: Salil Mehta <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/acpi/generic_event_device.c
Log Message:
-----------
hw/acpi: Update GED with vCPU Hotplug VMSD for migration
The ACPI CPU hotplug states must be migrated along with other vCPU
hotplug states to the destination VM. Update the GED's VM State
Description (VMSD) table subsection to conditionally include the CPU
Hotplug VM State Description (VMSD).
Excerpt of GED VMSD State Dump at Source:
"acpi-ged (16)": {
"ged_state": {
"sel": "0x00000000"
},
[...]
"acpi-ged/cpuhp": {
"cpuhp_state": {
"selector": "0x00000005",
"command": "0x00",
"devs": [
{
"is_inserting": false,
"is_removing": false,
"ost_event": "0x00000000",
"ost_status": "0x00000000"
},
[...]
{
"is_inserting": false,
"is_removing": false,
"ost_event": "0x00000000",
"ost_status": "0x00000000"
}
]
}
}
},
Signed-off-by: Salil Mehta <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: e70e83f561c45864eeb0945ae0298caa595262d2
https://github.com/qemu/qemu/commit/e70e83f561c45864eeb0945ae0298caa595262d2
Author: Zhenzhong Duan <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL
According to VTD spec, Figure 11-22, Invalidation Queue Tail Register,
"When Descriptor Width (DW) field in Invalidation Queue Address Register
(IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved
and a value of 1 in the bit will result in invalidation queue error."
Current code missed to send IQE event to guest, fix it.
Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
Suggested-by: Yi Liu <[email protected]>
Signed-off-by: Zhenzhong Duan <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 8e761fb61cafa95f4f41acaf8e86fae7e898b555
https://github.com/qemu/qemu/commit/8e761fb61cafa95f4f41acaf8e86fae7e898b555
Author: Zhenzhong Duan <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Add missed sanity check for 256-bit invalidation queue
According to VTD spec, a 256-bit descriptor will result in an invalid
descriptor error if submitted in an IQ that is setup to provide hardware
with 128-bit descriptors (IQA_REG.DW=0). Meanwhile, there are old inv desc
types (e.g. iotlb_inv_desc) that can be either 128bits or 256bits. If a
128-bit version of this descriptor is submitted into an IQ that is setup
to provide hardware with 256-bit descriptors will also result in an invalid
descriptor error.
The 2nd will be captured by the tail register update. So we only need to
focus on the 1st.
Because the reserved bit check between different types of invalidation desc
are common, so introduce a common function vtd_inv_desc_reserved_check()
to do all the checks and pass the differences as parameters.
With this change, need to replace error_report_once() call with error_report()
to catch different call sites. This isn't an issue as error_report_once()
here is mainly used to help debug guest error, but it only dumps once in
qemu life cycle and doesn't help much, we need error_report() instead.
Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
Suggested-by: Yi Liu <[email protected]>
Signed-off-by: Zhenzhong Duan <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 096d96e7be7071aa805c4e70ef51da0b99b6a8fc
https://github.com/qemu/qemu/commit/096d96e7be7071aa805c4e70ef51da0b99b6a8fc
Author: Zhenzhong Duan <[email protected]>
Date: 2024-11-04 (Mon, 04 Nov 2024)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Add missed reserved bit check for IEC descriptor
IEC descriptor is 128-bit invalidation descriptor, must be padded with
128-bits of 0s in the upper bytes to create a 256-bit descriptor when
the invalidation queue is configured for 256-bit descriptors (IQA_REG.DW=1).
Fixes: 02a2cbc872df ("x86-iommu: introduce IEC notifiers")
Signed-off-by: Zhenzhong Duan <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Commit: 9eb9350c0e519be97716f6b27f664bd0a3c41a36
https://github.com/qemu/qemu/commit/9eb9350c0e519be97716f6b27f664bd0a3c41a36
Author: Peter Maydell <[email protected]>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M docs/interop/vhost-user.rst
R hw/acpi/acpi_generic_initiator.c
M hw/acpi/aml-build.c
M hw/acpi/cpu.c
M hw/acpi/generic_event_device.c
M hw/acpi/meson.build
M hw/acpi/pci.c
M hw/arm/virt-acpi-build.c
M hw/block/vhost-user-blk.c
M hw/core/machine.c
M hw/cxl/cxl-mailbox-utils.c
M hw/i386/acpi-build.c
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/pc.c
M hw/mem/cxl_type3.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci-host/gpex-acpi.c
M hw/pci/pci.c
M hw/pci/pci_bridge.c
M hw/pci/pcie.c
M hw/virtio/vhost-user.c
M hw/virtio/virtio-pci.c
M include/exec/memory.h
R include/hw/acpi/acpi_generic_initiator.h
M include/hw/acpi/aml-build.h
M include/hw/acpi/pci.h
M include/hw/core/cpu.h
M include/hw/cxl/cxl_device.h
M include/hw/i386/intel_iommu.h
M include/hw/pci-bridge/cxl_upstream_port.h
M include/hw/pci/pci.h
M include/hw/pci/pci_bridge.h
M include/hw/pci/pci_device.h
M include/hw/pci/pcie.h
M include/hw/qdev-core.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/virtio-pci.h
M qapi/qdev.json
M qapi/qom.json
M system/qdev-monitor.c
M tests/data/acpi/disassemle-aml.sh
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.hpbrroot
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DSDT
M tests/data/acpi/x86/q35/DSDT.acpierst
M tests/data/acpi/x86/q35/DSDT.acpihmat
M tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/x86/q35/DSDT.applesmc
M tests/data/acpi/x86/q35/DSDT.bridge
M tests/data/acpi/x86/q35/DSDT.core-count
M tests/data/acpi/x86/q35/DSDT.core-count2
M tests/data/acpi/x86/q35/DSDT.cphp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.dimmpxm
M tests/data/acpi/x86/q35/DSDT.ipmibt
M tests/data/acpi/x86/q35/DSDT.ipmismbus
M tests/data/acpi/x86/q35/DSDT.ivrs
M tests/data/acpi/x86/q35/DSDT.memhp
M tests/data/acpi/x86/q35/DSDT.mmio64
M tests/data/acpi/x86/q35/DSDT.multi-bridge
M tests/data/acpi/x86/q35/DSDT.noacpihp
M tests/data/acpi/x86/q35/DSDT.nohpet
M tests/data/acpi/x86/q35/DSDT.numamem
M tests/data/acpi/x86/q35/DSDT.pvpanic-isa
M tests/data/acpi/x86/q35/DSDT.thread-count
M tests/data/acpi/x86/q35/DSDT.thread-count2
M tests/data/acpi/x86/q35/DSDT.tis.tpm12
M tests/data/acpi/x86/q35/DSDT.tis.tpm2
M tests/data/acpi/x86/q35/DSDT.type4-count
M tests/data/acpi/x86/q35/DSDT.viot
M tests/data/acpi/x86/q35/DSDT.xapic
A tests/qtest/fuzz-virtio-balloon-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, fixes, cleanups
CXL now can use Generic Port Affinity Structures.
CXL now allows control of link speed and width
vhost-user-blk now supports live resize, by means of
a new device-sync-config command
amd iommu now supports interrupt remapping
pcie devices now report extended tag field support
intel_iommu dropped support for Transient Mapping, to match VTD spec
arch agnostic ACPI infrastructure for vCPU Hotplug
Fixes, cleanups all over the place.
Signed-off-by: Michael S. Tsirkin <[email protected]>
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# gpg: Signature made Mon 04 Nov 2024 21:03:33 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "[email protected]"
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>" [full]
# gpg: aka "Michael S. Tsirkin <[email protected]>" [full]
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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (65
commits)
intel_iommu: Add missed reserved bit check for IEC descriptor
intel_iommu: Add missed sanity check for 256-bit invalidation queue
intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL
hw/acpi: Update GED with vCPU Hotplug VMSD for migration
tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35}
hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states
qtest: allow ACPI DSDT Table changes
hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug
hw/pci: Add parenthesis to PCI_BUILD_BDF macro
hw/cxl: Ensure there is enough data to read the input header in
cmd_get_physical_port_state()
hw/cxl: Ensure there is enough data for the header in cmd_ccls_set_lsa()
hw/cxl: Check that writes do not go beyond end of target attributes
hw/cxl: Ensuring enough data to read parameters in cmd_tunnel_management_cmd()
hw/cxl: Avoid accesses beyond the end of cel_log.
hw/cxl: Check the length of data requested fits in get_log()
hw/cxl: Check enough data in cmd_firmware_update_transfer()
hw/cxl: Check input length is large enough in cmd_events_clear_records()
hw/cxl: Check input includes at least the header in cmd_features_set_feature()
hw/cxl: Check size of input data to dynamic capacity mailbox commands
hw/cxl/cxl-mailbox-util: Fix output buffer index update when retrieving DC
extents
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/44a9394b1d27...9eb9350c0e51
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