Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 4253c980ea54b3cefc1a225feae35146e2ff6314
https://github.com/qemu/qemu/commit/4253c980ea54b3cefc1a225feae35146e2ff6314
Author: Jason Chien <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu.c: Correct the validness check of iova
>From RISCV IOMMU spec section 2.1.3:
When SXL is 1, the following rules apply:
- If the first-stage is not Bare, then a page fault corresponding to the
original access type occurs if the IOVA has bits beyond bit 31 set to 1.
- If the second-stage is not Bare, then a guest page fault corresponding
to the original access type occurs if the incoming GPA has bits beyond bit
33 set to 1.
>From RISCV IOMMU spec section 2.3 step 17:
Use the process specified in Section "Two-Stage Address Translation" of
the RISC-V Privileged specification to determine the GPA accessed by the
transaction.
>From RISCV IOMMU spec section 2.3 step 19:
Use the second-stage address translation process specified in Section
"Two-Stage Address Translation" of the RISC-V Privileged specification
to translate the GPA A to determine the SPA accessed by the transaction.
This commit adds the iova check with the following rules:
- For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero
extended.
- For Sv39, Sv48 and Sv57, the iova must be signed extended with most
significant bit.
Signed-off-by: Jason Chien <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2105538fa48b74be598f8aabdd9fea9d560ff73c
https://github.com/qemu/qemu/commit/2105538fa48b74be598f8aabdd9fea9d560ff73c
Author: Yong-Xuan Wang <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."
Update the riscv_aplic_set_pending() to match the spec.
Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for
APLIC MSI-mode")
Signed-off-by: Yong-Xuan Wang <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 18e353dfbb2637e7a19017f6ffb29396851aadc9
https://github.com/qemu/qemu/commit/18e353dfbb2637e7a19017f6ffb29396851aadc9
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.
With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra caps.
This will allow callers to add IOMMU capabilities before the
realization.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0249c16bbf46fae9c7b3281cd4ecc6cd8d136e71
https://github.com/qemu/qemu/commit/0249c16bbf46fae9c7b3281cd4ecc6cd8d136e71
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu-pci.c
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv-iommu.h
Log Message:
-----------
hw/riscv/riscv-iommu: parametrize CAP.IGS
Interrupt Generation Support (IGS) is a capability that is tied to the
interrupt deliver mechanism, not with the core IOMMU emulation. We
should allow device implementations to set IGS as they wish.
A new helper is added to make it easier for device impls to set IGS. Use
it in our existing IOMMU device (riscv-iommu-pci) to set
RISCV_IOMMU_CAPS_IGS_MSI.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ea60e63eefef8cc1daae8c92c4881c8d592949d0
https://github.com/qemu/qemu/commit/ea60e63eefef8cc1daae8c92c4881c8d592949d0
Author: Tomasz Jeznach <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/meson.build
A hw/riscv/riscv-iommu-sys.c
M hw/riscv/riscv-iommu.c
M include/hw/riscv/iommu.h
Log Message:
-----------
hw/riscv: add riscv-iommu-sys platform device
This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.
The WSIs are emitted using the input of the s->notify() callback as a
index to an IRQ list. The IRQ list starts at 'base_irq' and goes until
base_irq + 3. This means that boards must have 4 contiguous IRQ lines
available, starting from 'base_irq'.
Signed-off-by: Tomasz Jeznach <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 70348efc371fae210371a508ba4af58302d4e779
https://github.com/qemu/qemu/commit/70348efc371fae210371a508ba4af58302d4e779
Author: Sunil V L <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/iommu.h
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv/virt: Add IOMMU as platform device if the option is set
Add a new machine option called 'iommu-sys' that enables a
riscv-iommu-sys platform device for the 'virt' machine. The option is
default 'off'.
The device will use IRQs 36 to 39.
We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
the same board in this first implementation. If a riscv-iommu-pci device
is added in the command line we will disable the riscv-iommu-sys device.
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 513073bd3c49c4a3df3f605d8939b87b68923cfa
https://github.com/qemu/qemu/commit/513073bd3c49c4a3df3f605d8939b87b68923cfa
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/riscv-iommu-sys.c
M hw/riscv/trace-events
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
MSIx support is added in the RISC-V IOMMU platform device by including
the required MSIx facilities to alow software to properly setup the MSIx
subsystem.
We took inspiration of what is being done in the riscv-iommu-pci device,
mainly msix_init() and msix_notify(), while keeping in mind that
riscv-iommu-sys isn't a true PCI device and we don't need to copy/paste
all the contents of these MSIx functions.
Two extra MSI MemoryRegions were added: 'msix-table' and 'msix-pba'.
They are used to manage r/w of the MSI table and Pending Bit Array (PBA)
respectively. Both are subregions of the main IOMMU memory region,
iommu->regs_mr, initialized during riscv_iommu_realize(), and each one
has their own handlers for MSIx reads and writes.
This is the expected memory map when using this device in the 'virt'
machine:
0000000003010000-0000000003010fff (prio 0, i/o): riscv-iommu-regs
0000000003010300-000000000301034f (prio 0, i/o): msix-table
0000000003010400-0000000003010407 (prio 0, i/o): msix-pba
We're now able to set IGS to RISCV_IOMMU_CAP_IGS_BOTH, and userspace is
free to decide which interrupt model to use.
Enabling MSIx support for this device in the 'virt' machine requires
adding 'msi-parent' in the iommu-sys DT.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 99f3eaf6382a348b24f5ee7eb14d3b1772d66129
https://github.com/qemu/qemu/commit/99f3eaf6382a348b24f5ee7eb14d3b1772d66129
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/riscv-iommu-pci.c
M hw/riscv/riscv-iommu-sys.c
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv-iommu.h
M hw/riscv/trace-events
M include/hw/riscv/iommu.h
Log Message:
-----------
hw/riscv/riscv-iommu: implement reset protocol
Add a riscv_iommu_reset() helper in the base emulation code that
implements the expected reset behavior as defined by the riscv-iommu
spec.
Devices can then use this helper in their own reset callbacks.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 9d19fa3587cf9ef362c87f0b0a7bc4c4b5fa4817
https://github.com/qemu/qemu/commit/9d19fa3587cf9ef362c87f0b0a7bc4c4b5fa4817
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M docs/specs/riscv-iommu.rst
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/specs: add riscv-iommu-sys information
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f0916449eaa6ca5c701aeffe1382266ccd88ed9d
https://github.com/qemu/qemu/commit/f0916449eaa6ca5c701aeffe1382266ccd88ed9d
Author: Anton Blanchard <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add Tenstorrent Ascalon CPU
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0feb4511064447d8512390d6460e960c6c9222c0
https://github.com/qemu/qemu/commit/0feb4511064447d8512390d6460e960c6c9222c0
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/intc/riscv_aplic.c
M include/hw/intc/riscv_aplic.h
Log Message:
-----------
hw/intc/riscv_aplic: rename is_kvm_aia()
The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.
Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.
Make the helper public because the 'virt' machine will use it as well.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 44838e2da241066a55bb6ea2d274aa8521a9babd
https://github.com/qemu/qemu/commit/44838e2da241066a55bb6ea2d274aa8521a9babd
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
In create_fdt_sockets() we have the following pattern:
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do stuff ...)
} else {
(... do other stuff ...)
}
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do more stuff ...)
} else {
(... do more other stuff)
}
Do everything in a single if/else clause to reduce the usage of
virt_use_kvm_aia() helper and to make the code a bit less repetitive.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3f7a1eb6f528c0dc8c59a17cba4f58eb4848cfd4
https://github.com/qemu/qemu/commit/3f7a1eb6f528c0dc8c59a17cba4f58eb4848cfd4
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()
Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with
in-kernel irqchip enabled. It is not checking for a generic AIA support.
Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the
helper is doing, and use the existing riscv_is_kvm_aia_aplic_imsic() to
obscure details such as the presence of the in-kernel irqchip.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 9432390d5931d1a32a6f2f845e75a258a8e9177f
https://github.com/qemu/qemu/commit/9432390d5931d1a32a6f2f845e75a258a8e9177f
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: consider irqchip_split() in aia_create()
Before adding support to kernel-irqchip=split when using KVM AIA we need
to change how we create the in-kernel AIA device.
In the use case we have so far, i.e. in-kernel irqchip without split
mode, both the s-mode APLIC and IMSIC controllers are provided by the
irqchip. In irqchip_split() mode we'll emulate the s-mode APLIC
controller, which will send MSIs to the in-kernel IMSIC controller. To
do that we need to change kvm_riscv_aia_create() to not create the
in-kernel s-mode APLIC controller.
In the kernel source arch/riscv/kvm/aia_aplic.c, function
kvm_riscv_aia_aplic_init(), we verify that the APLIC controller won't be
instantiated by KVM if we do not set 'nr_sources', which is set via
KVM_DEV_RISCV_AIA_CONFIG_SRCS. For QEMU this means that we should not
set 'aia_irq_num' during kvm_riscv_aia_create() in irqchip_split() mode.
In this same condition, skip KVM_DEV_RISCV_AIA_ADDR_APLIC as well since
it is used to set the base address for the in-kernel APLIC controller.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 043fc4e45873fa9c280b490f0713f23b209bfb3b
https://github.com/qemu/qemu/commit/043fc4e45873fa9c280b490f0713f23b209bfb3b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/riscv/virt.c
M include/hw/intc/riscv_aplic.h
Log Message:
-----------
hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers
The current logic to determine if we don't need an emulated APLIC
controller, i.e. KVM will provide for us, is to determine if we're
running KVM, with in-kernel irqchip support, and running
aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
virt_use_kvm_aia_aplic_imsic().
This won't suffice to support irqchip_split() mode: it will match
exactly the same conditions as the one above, but setting the irqchip to
'split' mode will now require us to emulate an APLIC s-mode controller,
like we're doing with 'aia=aplic'.
Create a new riscv_use_emulated_aplic() helper that will encapsulate
this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with
this helper every time we're taking a decision on emulate an APLIC
controller or not. Do the same in virt.c with virt_use_emulated_aplic().
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a8b4fc1b83a0af5f8f2719722d285684d1f138b8
https://github.com/qemu/qemu/commit/a8b4fc1b83a0af5f8f2719722d285684d1f138b8
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/riscv/virt.c
M include/hw/intc/riscv_aplic.h
Log Message:
-----------
hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic
The last step to enable KVM AIA aplic-imsic with irqchip in split mode
is to deal with how MSIs are going to be sent. In our current design we
don't allow an APLIC controller to send MSIs unless it's on m-mode. And
we also do not allow Supervisor MSI address configuration via the
'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode
APLIC controller.
Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This
attribute represents the base configuration address for MSIs, in our
case the base addr of the IMSIC controller. This attribute is being set
only when running irqchip_split() mode with aia=aplic-imsic.
During riscv_aplic_msi_send() we'll check if the attribute was set to
skip the check for a m-mode APLIC controller and to change the resulting
MSI addr by adding kvm_msicfgaddr right before address_space_stl_le().
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2fff341f946e202bea123ff803e84c365d3ccceb
https://github.com/qemu/qemu/commit/2fff341f946e202bea123ff803e84c365d3ccceb
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: remove irqchip_split() restriction
Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
we have support for "-accel kvm,kernel-irqchip=split".
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6b72a9aa254987f361e2c8ea989e5b8f101c9996
https://github.com/qemu/qemu/commit/6b72a9aa254987f361e2c8ea989e5b8f101c9996
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M docs/specs/index.rst
A docs/specs/riscv-aia.rst
M docs/system/riscv/virt.rst
Log Message:
-----------
docs: update riscv/virt.rst with kernel-irqchip=split support
Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
the state of AIA support in QEMU w.r.t the controllers being emulated or
not depending on the AIA and accelerator settings.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ea2689d78d1ea34b116f747e096950405891fae5
https://github.com/qemu/qemu/commit/ea2689d78d1ea34b116f747e096950405891fae5
Author: Sai Pavan Boddu <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M MAINTAINERS
A docs/system/riscv/microblaze-v-generic.rst
M docs/system/target-riscv.rst
M hw/riscv/Kconfig
M hw/riscv/meson.build
A hw/riscv/microblaze-v-generic.c
Log Message:
-----------
hw/riscv: Add Microblaze V generic board
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial configuration is going beyond what it is
configured by default because validation should be done on other
configurations too. That's why wire also additional uart16500, axi
ethernet(with axi dma).
GPIOs, i2c and qspi is also listed for completeness.
IRQ map is: (addr)
0 - timer (0x41c00000)
1 - uartlite (0x40600000)
2 - i2c (0x40800000)
3 - qspi (0x44a00000)
4 - uart16550 (0x44a10000)
5 - emaclite (0x40e00000)
6 - timer2 (0x41c10000)
7 - axi emac (0x40c00000)
8 - axi dma (0x41e00000)
9 - axi dma
10 - gpio (0x40000000)
11 - gpio2 (0x40010000)
12 - gpio3 (0x40020000)
Signed-off-by: Sai Pavan Boddu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 91919b0be66a8d330016b89d214324ce0a19fcf2
https://github.com/qemu/qemu/commit/91919b0be66a8d330016b89d214324ce0a19fcf2
Author: Sia Jee Heng <[email protected]>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest: allow SPCR acpi table changes
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: fbb46a77b5bf50d1bc4207b1625dbe50ea138e64
https://github.com/qemu/qemu/commit/fbb46a77b5bf50d1bc4207b1625dbe50ea138e64
Author: Sia Jee Heng <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/acpi/aml-build.c
M hw/arm/virt-acpi-build.c
M hw/loongarch/acpi-build.c
M hw/riscv/virt-acpi-build.c
M include/hw/acpi/acpi-defs.h
M include/hw/acpi/aml-build.h
Log Message:
-----------
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 343df1e5bf4ae651336a680a46b8550aaa6c0dd4
https://github.com/qemu/qemu/commit/343df1e5bf4ae651336a680a46b8550aaa6c0dd4
Author: Sia Jee Heng <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M tests/data/acpi/riscv64/virt/SPCR
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Diffs from iasl:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Wed Aug 28 18:28:19 2024
+ * Disassembly of /tmp/aml-MN0NS2, Wed Aug 28 18:28:19 2024
*
* ACPI Data Table [SPCR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "SPCR" [Serial Port Console
Redirection table]
-[004h 0004 4] Table Length : 00000050
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : B9
+[004h 0004 4] Table Length : 0000005A
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 13
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 1] Interface Type : 00
+[024h 0036 1] Interface Type : 12
[025h 0037 3] Reserved : 000000
[028h 0040 12] Serial Port Register : [Generic Address Structure]
[028h 0040 1] Space ID : 00 [SystemMemory]
[029h 0041 1] Bit Width : 20
[02Ah 0042 1] Bit Offset : 00
[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
[02Ch 0044 8] Address : 0000000010000000
[034h 0052 1] Interrupt Type : 10
[035h 0053 1] PCAT-compatible IRQ : 00
[036h 0054 4] Interrupt : 0000000A
[03Ah 0058 1] Baud Rate : 07
[03Bh 0059 1] Parity : 00
[03Ch 0060 1] Stop Bits : 01
[03Dh 0061 1] Flow Control : 00
[03Eh 0062 1] Terminal Type : 00
[04Ch 0076 1] Reserved : 00
[040h 0064 2] PCI Device ID : FFFF
[042h 0066 2] PCI Vendor ID : FFFF
[044h 0068 1] PCI Bus : 00
[045h 0069 1] PCI Device : 00
[046h 0070 1] PCI Function : 00
[047h 0071 4] PCI Flags : 00000000
[04Bh 0075 1] PCI Segment : 00
-[04Ch 0076 4] Reserved : 00000000
+[04Ch 0076 004h] Uart Clock Freq : 00000000
+[050h 0080 004h] Precise Baud rate : 00000000
+[054h 0084 002h] NameSpaceStringLength : 0002
+[056h 0086 002h] NameSpaceStringOffset : 0058
+[058h 0088 002h] NamespaceString : "."
-Raw Table Data: Length 80 (0x50)
+Raw Table Data: Length 90 (0x5A)
- 0000: 53 50 43 52 50 00 00 00 02 B9 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20 // SPCRZ.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 00 00 00 00 00 20 00 01 00 00 00 10 // ......... ......
+ 0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10 // ......... ......
0030: 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 00 03 // ................
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 02 00 58 00 2E 00 // ......X...
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6727dfaf7f88b6790292ae5dc5055a17721f0b43
https://github.com/qemu/qemu/commit/6727dfaf7f88b6790292ae5dc5055a17721f0b43
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Cover RISC-V HTIF interface
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3124816bd3ade038be1627497a7465b5672b7f74
https://github.com/qemu/qemu/commit/3124816bd3ade038be1627497a7465b5672b7f74
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Explicit little-endian implementation
Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.
In that case tswap64() is equivalent to le64_to_cpu(), as in
"convert this 64-bit little-endian value into host cpu order".
Replace to simplify.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 51a7bf06431e558ee57fab5c7f4c451b3dc4375c
https://github.com/qemu/qemu/commit/51a7bf06431e558ee57fab5c7f4c451b3dc4375c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dc498dcef0a21064a971b569efc705f10cd5f490
https://github.com/qemu/qemu/commit/dc498dcef0a21064a971b569efc705f10cd5f490
Author: Jim Shu <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
[ Changes by AF
- Store fdt_load_addr_hi32 in the reset vector
]
Signed-off-by: Alistair Francis <[email protected]>
Commit: 458283f1899d154a1318f897a40931f7b03054a8
https://github.com/qemu/qemu/commit/458283f1899d154a1318f897a40931f7b03054a8
Author: Jim Shu <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Add a new struct RISCVBootInfo
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 36b862d25b20bb475fbb57cfd5ab94a9395c3819
https://github.com/qemu/qemu/commit/36b862d25b20bb475fbb57cfd5ab94a9395c3819
Author: Jim Shu <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M hw/riscv/boot.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Add the checking if DTB overlaps to kernel or initrd
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 65653102a3869b007f1b831404188199591c7faa
https://github.com/qemu/qemu/commit/65653102a3869b007f1b831404188199591c7faa
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add svukte extension capability variable
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 1d6ca4711ac8e2a71862c361cef14e38bcd9e9c8
https://github.com/qemu/qemu/commit/1d6ca4711ac8e2a71862c361cef14e38bcd9e9c8
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].
Signed-off-by: Fea.Wang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c6f98f996dcabbd7a15e1968ac1ddb0474cb6d46
https://github.com/qemu/qemu/commit/c6f98f996dcabbd7a15e1968ac1ddb0474cb6d46
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 1f6cf1814bf3f3ce6f342485f7a4bc5375be0afa
https://github.com/qemu/qemu/commit/1f6cf1814bf3f3ce6f342485f7a4bc5375be0afa
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Check memory access to meet svukte rule
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.
Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Fea.Wang <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 906057313d22488e89402efea41c6c453dc8db46
https://github.com/qemu/qemu/commit/906057313d22488e89402efea41c6c453dc8db46
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose svukte ISA extension
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f4d8c686a663b90d295a192c143cbd9e821e356e
https://github.com/qemu/qemu/commit/f4d8c686a663b90d295a192c143cbd9e821e356e
Author: Fea.Wang <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Check svukte is not enabled in RV32
The spec explicitly says svukte doesn't support RV32. So check that it
is not enabled in RV32.
Signed-off-by: Fea.Wang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5f3d53fdbe8ea2c4ade95e8bf939f7234fdd173e
https://github.com/qemu/qemu/commit/5f3d53fdbe8ea2c4ade95e8bf939f7234fdd173e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: Include missing headers in 'vector_internals.h'
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/vector_internals.h:36:12: error: call to undeclared function
'FIELD_EX32'; ISO C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
36 | return FIELD_EX32(simd_data(desc), VDATA, NF);
| ^
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 64f3c103877b593c15b99aca36508f2ef8334e87
https://github.com/qemu/qemu/commit/64f3c103877b593c15b99aca36508f2ef8334e87
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Include missing headers in 'internals.h'
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
49 | ret = PRV_S;
| ^
target/riscv/internals.h:93:9: error: call to undeclared function
'env_archcpu'; ISO C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
93 | if (env_archcpu(env)->cfg.ext_zfinx) {
| ^
target/riscv/internals.h:101:15: error: unknown type name 'float32'; did you
mean 'float'?
101 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
| ^~~~~~~
| float
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 50ab5dcd6ec5f889f250d06f95a2d9898744285d
https://github.com/qemu/qemu/commit/50ab5dcd6ec5f889f250d06f95a2d9898744285d
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: hide warn for named feats when disabling via priv_ver
Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to disable zic64b
manually in riscv_cpu_update_named_features().
This solution won't scale well when adding more named features, and can
eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().
Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
disabling a named feature. This will accomplish the same thing we're
doing today while avoiding having two points where we're disabling
exts via priv_ver mismatch.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 47d1d1fa57fa770040f299ffbe44b735b48d11ec
https://github.com/qemu/qemu/commit/47d1d1fa57fa770040f299ffbe44b735b48d11ec
Author: Daniel Henrique Barboza <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: add ssstateen
ssstateen is defined in RVA22 as:
"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."
Add ssstateen as a named feature that is available if we also have
smstateen.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5632d271be16b5e769342d54198c4359658abcb7
https://github.com/qemu/qemu/commit/5632d271be16b5e769342d54198c4359658abcb7
Author: MollyChen <[email protected]>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add support for RV64 Xiangshan Nanhu CPU
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
[ Changes by AF
- Fixup code formatting
]
Signed-off-by: Alistair Francis <[email protected]>
Commit: deeca9cb0ba8d8c85e2b8eeb778b35dd0b806d8c
https://github.com/qemu/qemu/commit/deeca9cb0ba8d8c85e2b8eeb778b35dd0b806d8c
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M include/hw/intc/loongarch_pch_pic.h
A include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
include: Add loongarch_pic_common header file
Add common header file hw/intc/loongarch_pic_common.h, and move
some macro definition from hw/intc/loongarch_pch_pic.h to the common
header file.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: f58ac9784728e27b096f4d0086f5277a7bef01f4
https://github.com/qemu/qemu/commit/f58ac9784728e27b096f4d0086f5277a7bef01f4
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M include/hw/intc/loongarch_pch_pic.h
M include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
to file loongarch_pic_common.h, and rename structure name with
LoongArchPICCommonState.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: f42e88883745ddf4ab48c26253d2dfb7f76a3f53
https://github.com/qemu/qemu/commit/f42e88883745ddf4ab48c26253d2dfb7f76a3f53
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pch_pic.c
Log Message:
-----------
hw/intc/loongarch_pch: Merge instance_init() into realize()
Memory region is created in instance_init(), merge it into function
realize(). There is no special class_init() for loongarch_pch object.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: c43aceddb292229fa9206b8e26fb65a92dd90562
https://github.com/qemu/qemu/commit/c43aceddb292229fa9206b8e26fb65a92dd90562
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pch_pic.c
Log Message:
-----------
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
vmstate_loongarch_pic_common, and with pic property rename
loongarch_pch_pic_properties with loongarch_pic_common_properties.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: b7563779f9e3a319af1a8d39084d0342e5dbb1bb
https://github.com/qemu/qemu/commit/b7563779f9e3a319af1a8d39084d0342e5dbb1bb
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pch_pic.c
A hw/intc/loongarch_pic_common.c
Log Message:
-----------
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
Move some common functions to file loongarch_pic_common.c, the common
functions include loongarch_pic_common_realize(), property structure
loongarch_pic_common_properties and vmstate structure
vmstate_loongarch_pic_common.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 8bf26a9ea3c8067e04c36b0280b219958955196c
https://github.com/qemu/qemu/commit/8bf26a9ea3c8067e04c36b0280b219958955196c
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pch_pic.c
M hw/intc/loongarch_pic_common.c
M hw/intc/meson.build
M include/hw/intc/loongarch_pch_pic.h
M include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
its own realize() function.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 36d31cf812848ee65ab03ca901e7b140f5538a7a
https://github.com/qemu/qemu/commit/36d31cf812848ee65ab03ca901e7b140f5538a7a
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pic_common.c
M include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
Add vmstate pre_save and post_load interfaces, which can be used
by pic kvm driver in future.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: b2799f101cfb58f46cd5ef043038276d128d8e72
https://github.com/qemu/qemu/commit/b2799f101cfb58f46cd5ef043038276d128d8e72
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_pch_pic.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_pch_pic.h
Log Message:
-----------
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
separately. Also remove unnecessary header files.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: fea46db1c7f3b7cd3df92e871c10a6b85a872041
https://github.com/qemu/qemu/commit/fea46db1c7f3b7cd3df92e871c10a6b85a872041
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M include/hw/intc/loongarch_extioi.h
A include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
include: Add loongarch_extioi_common header file
Add common header file include/hw/intc/loongarch_extioi_common.h, and
move some macro definition from include/hw/intc/loongarch_extioi.h to
the common header file.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 593c6b868450603a3295892d8d65b1eba4ea211d
https://github.com/qemu/qemu/commit/593c6b868450603a3295892d8d65b1eba4ea211d
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M include/hw/intc/loongarch_extioi.h
M include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
to file loongarch_extioi_common.h.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 6f54d920935826a3ce47ba64605b3ccd20d9c0f1
https://github.com/qemu/qemu/commit/6f54d920935826a3ce47ba64605b3ccd20d9c0f1
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M include/hw/intc/loongarch_extioi.h
M include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
since it is defined in file loongarch_extioi_common.h
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: c169b51b1720c2722bfacb83896cd7100859ee4c
https://github.com/qemu/qemu/commit/c169b51b1720c2722bfacb83896cd7100859ee4c
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
Log Message:
-----------
hw/intc/loongarch_extioi: Rename LoongArchExtIOI with
LoongArchExtIOICommonState
With some structure such as vmstate and property, rename LoongArchExtIOI
with LoongArchExtIOICommonState, these common structure will be moved
to common file.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: aa6330d50ccf7467a022dc348ab6ae2323c2b0b9
https://github.com/qemu/qemu/commit/aa6330d50ccf7467a022dc348ab6ae2323c2b0b9
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
Log Message:
-----------
hw/intc/loongarch_extioi: Add common realize interface
Add common realize function, it is only to check validity of property.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 4abf47126f5c37e974c58f3cbd295abcc67b8668
https://github.com/qemu/qemu/commit/4abf47126f5c37e974c58f3cbd295abcc67b8668
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
Log Message:
-----------
hw/intc/loongarch_extioi: Add unrealize interface
For loongarch extioi emulation driver, add unrealize interface and
remove instance_finalize interface and move the code to unrealize
interface.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 6b69f778176d6d00842ec4e7ac9400af1620387a
https://github.com/qemu/qemu/commit/6b69f778176d6d00842ec4e7ac9400af1620387a
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
A hw/intc/loongarch_extioi_common.c
Log Message:
-----------
hw/intc/loongarch_extioi: Add common file loongarch_extioi_common
Add new common file loongarch_extioi_common.c, and move vmstate
and property structure to common file.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 272c467a48815e77db89b69dcd251b9f5b22203e
https://github.com/qemu/qemu/commit/272c467a48815e77db89b69dcd251b9f5b22203e
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
M hw/intc/loongarch_extioi_common.c
M hw/intc/meson.build
M include/hw/intc/loongarch_extioi.h
M include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
hw/intc/loongarch_extioi: Inherit from loongarch_extioi_common
Set TYPE_LOONGARCH_EXTIOI inherit from TYPE_LOONGARCH_EXTIOI_COMMON
object, it shares vmsate and property of TYPE_LOONGARCH_EXTIOI_COMMON,
and has its own realize() function.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: ff09444a88af9f5d55b9e315aa16d3ace1f25211
https://github.com/qemu/qemu/commit/ff09444a88af9f5d55b9e315aa16d3ace1f25211
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi_common.c
M include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
hw/intc/loongarch_extioi: Add pre_save interface
Add vmstate pre_save interface, which can be used extioi kvm driver
in future.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 6f6006ad07243543595c7607ffbeee7f45b94b80
https://github.com/qemu/qemu/commit/6f6006ad07243543595c7607ffbeee7f45b94b80
Author: Bibo Mao <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
M include/hw/intc/loongarch_extioi.h
Log Message:
-----------
hw/intc/loongarch_extioi: Code cleanup about loongarch_extioi
Remove definition about LoongArchExtIOI and LOONGARCH_EXTIOI, and
replace them with LoongArchExtIOICommonState and macro
LOONGARCH_EXTIOI_COMMON separately. Also remove unnecessary header
files.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: afded726d920a6b241ce74534289b6c6c5fa75b0
https://github.com/qemu/qemu/commit/afded726d920a6b241ce74534289b6c6c5fa75b0
Author: Stefan Hajnoczi <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M MAINTAINERS
M docs/specs/index.rst
A docs/specs/riscv-aia.rst
M docs/specs/riscv-iommu.rst
A docs/system/riscv/microblaze-v-generic.rst
M docs/system/riscv/virt.rst
M docs/system/target-riscv.rst
M hw/acpi/aml-build.c
M hw/arm/virt-acpi-build.c
M hw/char/riscv_htif.c
M hw/intc/riscv_aplic.c
M hw/loongarch/acpi-build.c
M hw/riscv/Kconfig
M hw/riscv/boot.c
M hw/riscv/meson.build
A hw/riscv/microblaze-v-generic.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu-pci.c
A hw/riscv/riscv-iommu-sys.c
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv-iommu.h
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/trace-events
M hw/riscv/virt-acpi-build.c
M hw/riscv/virt.c
M include/hw/acpi/acpi-defs.h
M include/hw/acpi/aml-build.h
M include/hw/intc/riscv_aplic.h
M include/hw/riscv/boot.h
M include/hw/riscv/iommu.h
M include/hw/riscv/virt.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/internals.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/vector_internals.h
M tests/data/acpi/riscv64/virt/SPCR
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20241219-1' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 10.0
* Correct the validness check of iova
* Fix APLIC in_clrip and clripnum write emulation
* Support riscv-iommu-sys device
* Add Tenstorrent Ascalon CPU
* Add AIA userspace irqchip_split support
* Add Microblaze V generic board
* Upgrade ACPI SPCR table to support SPCR table revision 4 format
* Remove tswap64() calls from HTIF
* Support 64-bit address of initrd
* Introduce svukte ISA extension
* Support ssstateen extension
* Support for RV64 Xiangshan Nanhu CPU
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# gpg: Signature made Wed 18 Dec 2024 17:27:09 EST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20241219-1' of https://github.com/alistair23/qemu:
(39 commits)
target/riscv: add support for RV64 Xiangshan Nanhu CPU
target/riscv: add ssstateen
target/riscv/tcg: hide warn for named feats when disabling via priv_ver
target/riscv: Include missing headers in 'internals.h'
target/riscv: Include missing headers in 'vector_internals.h'
target/riscv: Check svukte is not enabled in RV32
target/riscv: Expose svukte ISA extension
target/riscv: Check memory access to meet svukte rule
target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
target/riscv: Add svukte extension capability variable
hw/riscv: Add the checking if DTB overlaps to kernel or initrd
hw/riscv: Add a new struct RISCVBootInfo
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
hw/char/riscv_htif: Explicit little-endian implementation
MAINTAINERS: Cover RISC-V HTIF interface
tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
qtest: allow SPCR acpi table changes
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: d7d215f75fb36cb5039199c390d8cc0ed71145d9
https://github.com/qemu/qemu/commit/d7d215f75fb36cb5039199c390d8cc0ed71145d9
Author: Stefan Hajnoczi <[email protected]>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M hw/intc/loongarch_extioi.c
A hw/intc/loongarch_extioi_common.c
M hw/intc/loongarch_pch_pic.c
A hw/intc/loongarch_pic_common.c
M hw/intc/meson.build
M hw/loongarch/virt.c
M include/hw/intc/loongarch_extioi.h
A include/hw/intc/loongarch_extioi_common.h
M include/hw/intc/loongarch_pch_pic.h
A include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
Merge tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu into
staging
loongarch queue
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# gpg: Signature made Thu 19 Dec 2024 02:23:49 EST
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu:
hw/intc/loongarch_extioi: Code cleanup about loongarch_extioi
hw/intc/loongarch_extioi: Add pre_save interface
hw/intc/loongarch_extioi: Inherit from loongarch_extioi_common
hw/intc/loongarch_extioi: Add common file loongarch_extioi_common
hw/intc/loongarch_extioi: Add unrealize interface
hw/intc/loongarch_extioi: Add common realize interface
hw/intc/loongarch_extioi: Rename LoongArchExtIOI with
LoongArchExtIOICommonState
include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
include: Add loongarch_extioi_common header file
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
hw/intc/loongarch_pch: Merge instance_init() into realize()
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
include: Add loongarch_pic_common header file
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/3e9793ab0190...d7d215f75fb3
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